Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-03-23
2001-07-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S229000
Reexamination Certificate
active
06269046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having row and column decoders for decoding row and column address signals without generating leakage current in stand-by mode.
2. Description of the Related Art
A semiconductor memory device includes a memory cell array, a row decoder, a column decoder, sense amplifiers and data input/output lines. A memory cell array includes a plurality of memory cells connecting with word lines and pairs of bit lines for accessing data in the memory cells. The pairs of bit lines are electrically connected to the sense amplifiers under control of column selection lines from a column decoder. A row decoder decodes a row address signal received from an external source to select some of the word lines. A column decoder decodes a column address signal received from an external source to select some of the column selection lines. The row decoder is connected to drivers to drive the word lines, and the column decoder is connected to drivers to drive the column selection lines.
In a semiconductor memory device utilizing a low supply voltage, the widths of the gates of MOS (metal oxide semiconductor) transistors in row and column decoders are very small. Thus, when a slight voltage difference exists between a source and a drain of a MOS transistor while the row and column decoders are in a stand-by state, a small leakage current is generated from the MOS transistor. Since the amount of such leakage current is small, the leakage current little affects power consumption of a semiconductor memory device when the number of row and column decoders in the semiconductor memory device is small. However, the amount of leakage current increases with an increase in the number of row and column decoders in a semiconductor memory device, so that power consumption of the semiconductor memory device also increases. As larger semiconductor devices are used in applications with finite power sources, such as portable or laptop computers, the larger leakage current becomes a factor affecting performance and/or appeal.
Therefore, it would be advantageous to provide a semiconductor device having decoders for decoding row and column address signals which do not generate leakage current in a stand-by state, thereby reducing power consumption of the semiconductor device. It is also desirable to provide a semiconductor device with improved row and column decoders which do not affect the size of the semiconductor device, even in a high-integrated semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device having a row address decoding unit which does not generate leakage current. The semiconductor memory device may utilize a low internal supply voltage.
Another object of the present invention is to provide a semiconductor memory device having a column address decoding unit which does not generate leakage current. The semiconductor memory device may also utilize a low internal supply voltage.
In an aspect of the present invention, there is provided a semiconductor device having a plurality of memory cells connecting with a plurality of word lines, comprising a power supply voltage (Vcc) applied to the semiconductor device, a row controller for generating an output signal in response to a control signal representing one of a normal operation state and a stand-by state, and a plurality of row decoders connected between the row controller and the plurality of word lines, wherein each row decoder activates a corresponding word line in response to the output signal from the row controller and a row address signal from an external source, and the output signal of the row controller is a high voltage when the plurality of row decoders are in a normal operation state, and the output signal is a ground voltage when the plurality of row decoders are in a stand-by state. Each of the plurality of row decoders comprises a pull-up portion receiving the output signal from the row controller, for generating the high voltage when the output signal of the row controller is the high voltage, a decoding portion coupled to the pull-up portion, for receiving the row address signal and decoding the received row address signal, a latch portion coupled to a node to which the pull-up portion and the decoding portion are coupled, for latching the corresponding word line of the plurality of word lines to logic low when a voltage level of the node is a first voltage level, and a driver coupled to the node and the row controller, for activating the corresponding word line when the voltage level of the node is a second voltage level, and making the corresponding word line inactive when the voltage level of the node is the first voltage level, wherein an input of the driver receives the output signal from the row controller.
According to another aspect of the present invention, a semiconductor device having a plurality of memory cells connecting with a plurality of bit line pairs which are selectively connected to corresponding input/output line pairs in response to a plurality of column selection lines to transfer data from/to an external source, comprises a column controller for receiving an internal supply voltage and for generating an output signal in response to a first control signal representing one of a normal operation state and a standby state, and a plurality of column decoders connected between the column controller and a plurality of column selection lines, wherein each column decoder activates a corresponding column selection line in response to the output signal from the column controller, a column address signal, and the output signal of the column controller is the internal supply voltage when the plurality of column decoders are in a normal operation state and is a ground voltage when the plurality of column decoders are in a stand-by state. Each column decoder comprises a pull-up portion for receiving the second control signal and outputting the internal supply voltage when the second control signal represents the stand-by state, a decoding portion coupled to an output of the pull-up portion, for providing the ground voltage at the output of the pull-up portion in response to the column address signal, a latch portion coupled to the output of the pull-up portion, for latching the corresponding column selection line to the ground voltage when the plurality of column decoders are in the standby state, and a driver coupled to the output of the pull-up portion and the column controller, for activating the corresponding column selection line when the plurality of column decoders are in the normal operation state.
Therefore, power consumption of the semiconductor memory device using a low internal supply voltage is decreased.
REFERENCES:
patent: 5392253 (1995-02-01), Atsumi et al.
Kawahara, et al., “Subthreshold Current Reduction for Decoded-Drive by Self-Reverse Biasing”, IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993.
Byun Sang-man
Lee Kyu-Chan
F. Chau & Associates LLP
Lam David
Nelms David
Samsung Electronics Co,. Ltd.
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