Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1995-03-16
1999-05-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711118, G06F12/08
Patent
active
059039159
ABSTRACT:
An automatic method and apparatus in a computer system of cache detection. Accessing of data stored at first specified boundaries in a memory of the computer system corresponding with a first size of a cache is timed to produce a first timing value. Accessing of data stored at second specified boundaries in the memory of the computer system corresponding with a second size of a cache which is greater than the first size is timed to produce a second timing value. If the second timing value exceeds the first timing value by a threshold then the presence of a cache of the first size is indicated. This can also be performed iteratively until the memory of computer system has been completely tested for the presence of any caches. The process may be performed for instruction or data caches wherein the accessing of data for data caches includes memory access instruction, and the accessing of data for instruction caches includes the execution of instructions. Methods and apparatus for determining other cache characteristics are also described including detecting the set associativity of any known caches, and whether the known data and instruction caches are unified or not.
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Chan Eddie P.
Intel Corporation
Portka Gary J.
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