Memory access limiter for random access dynamic memories

Details Memory access limiter for random access dynamic memories Memory access limiter for random access dynamic memories

1996-11-27

1999-05-11

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 711104, 39575002, 39575008, 365226, 365227, 365228, 365195, G06F12/14

Patent

active

059039140

ABSTRACT:
A memory access limiter for random access dynamic memory of data processing systems formed by several modules which can be independently activated in partial temporal superimposition, each by a memory start command, comprising a bidirectional counter which periodically increments at a constant period defined by a clock signal, by a value representative of the electrical charge delivered by a power supply to an output buffer capacitor and decrements, at each memory start command, by a value representative of the electrical charge drained at each memory operation activated by the memory start command, a predetermined decremented count state of the counter identifying a maximum admissible discharge condition of the buffer capacitor below which it is necessary to inhibit any further activation of the memory until the count state of the counter is no longer below the predetermined count state.

REFERENCES:
patent: 4700330 (1987-10-01), Altman et al.
patent: 5148546 (1992-09-01), Blodgett
patent: 5168206 (1992-12-01), Jones
patent: 5182810 (1993-01-01), Barting et al.
patent: 5404543 (1995-04-01), Faucher et al.
patent: 5765219 (1998-06-01), Densham et al.

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