Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-08-31
2001-12-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000, C365S222000, C714S746000, C714S754000
Reexamination Certificate
active
06334167
ABSTRACT:
BACKGROUND OF THE INVENTION
CROSS REFERENCES TO RELATED APPLICATIONS
U.S. patent application Ser. No. 09/144,248, entitled “System and Method for Memory Scrub During Self Timed Refresh”, filed concurrently herewith is assigned to the same assignee hereof and contains subject matter related, in certain respect, to the subject matter of the present application. The above-identified patent application is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
This invention relates to refresh of memory subsystems. More particularly, it relates to reduced power memory refresh of SDRAM memory subsystems.
BACKGROUND ART
Dynamic Random Access Memory (DRAM) chips need to have the charge in their array cells periodically refreshed to retain the data contents. This refresh is normally initiated by commands issued by a memory controller external to the DRAMs. Synchronous DRAMs (SDRAMS) provide a mode, Self-Timed Refresh (STR) mode, during which the SDRAM initiates refresh internally provided no read or write accesses to memory occur. Computer SDRAM memory subsystems utilize less power for STR mode verses externally initiated refresh. However, energy is wasted when an SDRAM is not actively being accessed to read or write data but is still kept fully powered and periodically refreshed via externally issued refresh.
It is an object of the invention to provide improved, energy efficient memory refresh system and method.
SUMMARY OF THE INVENTION
In accordance with the invention, a memory controller for a synchronous dynamic random access memory (SDRAM) is provided which, upon detecting an interval of memory inactivity, halts external refresh commands, initiates self timed refresh (STR) mode, and, upon detecting a read or write operation, exits STR mode.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
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Gerchman Edward T.
Gildea Mark C.
Hovis William P.
Jensen Randall S.
Maule Warren E.
Anderson Matthew D.
Beckstrand Shelly M
International Business Machines - Corporation
Kim Matthew
LandOfFree
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