Source/drain and lightly doped drain formation at post...

Details Source/drain and lightly doped drain formation at post... Source/drain and lightly doped drain formation at post...

1998-04-16

2001-01-09

Wojchiechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S412000, C257S413000, C257S513000, C257S514000, C257S754000

Reexamination Certificate

active

06172407

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for forming source and drain implant areas and salicidation after deposition of an interlevel dielectric.
2. Description of the Related Art
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V
T
. Several factors contribute to V
T
, one of which is the effective channel length (“L
eff
”) of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. After implantation and subsequent diffusion of the junctions, however, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length decreases, so too must L
eff
. Decreasing L
eff
reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L
eff
. Accordingly, reducing L, and hence L
eff
, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L
eff
is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Minimizing L also improves the speed of integrated circuits including a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from a device operation standpoint. In addition, minimizing L is desirable from a manufacturing perspective, because a smaller area of silicon is required to manufacture a transistor having a smaller length.
As the gate conductor decreases in lateral dimension, the contact resistance increases, as does the sheet resistivity of the shallow junctions of the source and drain regions. To reduce these resistance values, along with reducing the interconnect resistance of the polysilicon gate conductors, self-aligned silicide (“salicide”) technology can be used. Using the salicide technique, a refractory metal is deposited over an MOS structure. The metal is then heated and reacted with the exposed silicon of the source and drain areas and the exposed polysilicon areas of the gate to form a metal silicide. Dielectric spacers are typically formed adjacent the sidewalls of the polysilicon gate conductor from, e.g., silicon dioxide. Because the spacers substantially inhibit formation of the silicide, the spacers prevent the source and drain areas from becoming electrically connected to the gate.
The difficulty in forming a metal silicide increases as the gate width decreases. Refractory metal is usually deposited as a conformal layer across the semiconductor topography. The thickness of the metal layer may be insufficient on very narrow gates to allow adequate silicide formation (the so-called “narrow poly effect”). If the thickness of the deposited metal is increased, however, the thickness of the silicide formed on the source and drain regions may exceed the depth of the junction, leading to electrical shorting of the device, or “junction spiking”.
Other features of MOS transistors have also grown smaller as the gate length has decreased. For example, the thickness of the gate dielectric is made as small as possible, because the drive current in MOSFETs increases with decreasing gate dielectric thickness. In addition, thin gate dielectrics control short channel effects by permitting the gate to retain control of the channel charge. Typically, the gate dielectric is a layer of silicon dioxide (“oxide”). The use of very thin gate oxides may present several potential problems, however. It is at present difficult to grow very thin gate dielectric oxides precisely and uniformly across a semiconductor substrate and from wafer to wafer. The gate oxide must also be resistant to breakdown and hot-carrier damage. In p-channel devices, the gate oxide needs to be resistant to penetration by boron at the processing temperatures used after gate doping.
It would therefore be desirable to derive a method for fabricating a transistor in which a salicide can be formed across a narrow gate without the risk of junction spiking. It would further be desirable to form a narrow-gate-width device without the disadvantages associated with thin gate dielectrics.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for fabricating a transistor in which source and drain implant areas and metal silicides are formed following deposition of an interlevel dielectric. In one embodiment, a layer of a high-K dielectric material is formed upon a semiconductor substrate. For purposes of this application, a “high-K dielectric material” is a material having a dielectric constant K greater than approximately 3.8, the K value of silicon dioxide. Examples of high-K dielectrics include barium strontium titanate, lead lanthanum zirconate titanate, barium zirconate titanate, cerium oxide, tin oxide, and tantalum oxide. The high-K dielectric layer may be formed using, e.g., chemical vapor deposition (“CVD”) or spin-on deposition.
A conductive gate layer is subsequently deposited across the high-K dielectric layer. The conductive gate layer is preferably polysilicon that has been chemically-vapor deposited (“CVD”) from, e.g., a silane source. However, the conductive gate layer may include other semiconductive or conductive materials. Following formation of the dielectric and conductive gate layers, a gate electrode having opposed sidewall surfaces may be defined by etching portions of the conductive gate layer and the dielectric layer not covered by a patterned photoresist layer using, e.g., a directional plasma etch technique.
In an embodiment of the present invention in which the high-K gate dielectric is deposited to a thickness of substantially greater than approximately 500 angstroms, an interlevel dielectric material may be deposited across the semiconductor topography following formation of the gate structure and an upper surface of the interlevel dielectric polished to form a substantially planar upper surface. For purposes of this application, an “interlevel dielectric” is a dielectric material which exists in a plane above a semiconductor substrate and typically functions to electrically isolate two conductive layers (e.g., a gate conductor and a level of interconnect). An interlevel dielectric is distinguishable from a field dielectric. A “field dielectric” or “isolation region” is typically formed within, rather than upon, a semiconductor substrate and functions to electrically isolate active regions of the semiconductor substrate from one another. The interlevel dielectric may include, e.g., silicon dioxide deposited from a TEOS source. A layer of photoresist may then be deposited across the upper surface of the interlevel dielectric. Portions of the photoresist above the active regions of the semiconductor substrate may be patterned using optical lithography. Interlevel dielectric material may then be selectively removed to form an opening exposing the gate structure and the source and drain regions. Following formation of the opening, the photoresist may be stripped from the upper surface of remaining portions of the interlevel dielectric. Alternatively, the photoresist may be retained upon the interlevel dielectric and removed at a subsequent processing step.
An implant impurity distribution may then be forwarded into the semiconductor substrate, with the gate dielectric and the gate conductor serving as implant masks to block implantation of impurity ions into the channel region underlying the gate. Heavily doped source and drain reg

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