Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-31
2001-07-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S546000, C257S547000
Reexamination Certificate
active
06259139
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a structure of MOS ESD (electrostatic discharge) protection circuit. And more specifically, this invention relates to a MOS ESD protection circuit that minimizes heating effect by embedded well diode.
2. Description of the Prior Art
Electrostatic discharge phenomena in integrated circuits have grown in importance as technologies shrink to below 0.5 microns and the number of transistors on a single chip approach the 5 million mark. The high voltages result in large electrical fields and high current densities in the small devices that can lead to breakdown of insulators and thermal damage in the integrated circuits. Therefore, ESD protection circuit is necessary for integrated circuits and then introduction of each new generation of semiconductor technology results in new challenges in terms of ESD capability and protection circuit design.
The relation between other parts of integrated circuits and an ESD protection circuit that used to protect chips from external charge/voltage is shown in FIG.
1
. As
FIG. 1
shows, external current (charger) is conducted from terminal
10
through internal buffer
12
to internal chips
13
, and internal current (charger) is conducted from internal chips
13
through internal buffer
12
to terminal
10
. However, because larger external current will induce unexpected damage on internal chips
13
, ESD protection circuits
11
are used where ESD protection circuits
11
are located between terminal
10
and internal buffer
12
. Moreover, ESD protection circuits
11
are turn-off when no larger external current is appeared, and when larger external current appears ESD protection circuits
11
are turned on automatically. Therefore, larger external current is conducted to VDD
14
and VSS
15
, and internal chips
13
are not damaged.
There are many varieties of ESD protect circuit, and one useful variety of ESD protection circuits is the metal-oxide-semiconductor (MOS) protect circuit that uses MOS transistor to form required ESD protection circuit. Herein, advantages of MOS ESD protection circuit include high integration and high reliability. Significantly, when integration of integrated circuits are increased, MOS ESD protection circuit is more attractive for it can reduce occupied area of ESD protection circuit to further increase integration.
As the cross-sectional figure shown in
FIG. 2A
where conventional structure of MOS ESD protection circuit is qualitative illustrated. The MOS ESD protection circuit is form in and on well
22
, and is surrounded by isolation
21
to prevent the protection circuit is interfered with other parts of substrate
20
. Herein, a plurality of MOS transistors are located in and on well
22
, and these MOS transistors are surrounded by guard ring
26
. Moreover, drains
24
are coupled to terminal
27
by first conductive lines
28
, and sources
23
, gates
25
and guard ring
26
are coupled to relative ground point
295
by second conductive line
29
. Beside, conventional layout of MOS ESD protection circuit is qualitative illustrated in
FIG. 2B
, where
FIG. 2A
is a cross-sectional illustration along AA line. Moreover, relative ground point
295
usually is provided by substrate
20
.
Mechanism of the MOS ESD protection circuit can briefly described as following: when chargers is appeared on terminal
27
and more then threshold value of the MOS ESD protection circuit, they are conducted to drains
24
by first conductive lines
28
. Then, owing to the fact extra charges induce electrical field and alter distribution of charge carriers inside substrate
20
and well
22
, some parasitic bipolar junction transistors that located under drains
24
and sources
23
are formed, and then extra chargers are conducted grounded point
295
. One advantages of MOS ESD protection circuit is that current gain of bipolar junction transistors can enhance the protect ability of ESD protection circuit. Moreover, numerous parasitic diodes are formed under gates
25
. Thus, though trigger time of bipolar junction transistors is slow, before parasitic bipolar junction transistors are triggered, extra chargers also are conducted to grounded point
295
by parasitic diodes and first conductive lines
29
.
However, an unavoidable deficiency of conventional MOS ESD protection circuit is that parasitic diodes induce a large electrical field on depletion region that around both sources
23
and drains
24
. Therefore, owing to high electrical field may induce quantities of heat, it is possible that parasitic diodes are overburning by heat before so-called parasitic bipolar junction transistors are triggered, and then ESD protection circuit can not properly protect chips inside integrated circuits, even parasitic bipolar junction transistors are triggered later.
In summary, because conventional MOS ESD protection circuit faces the issue that parasitic diodes are destroyed before parasitic bipolar junction transistors are triggered, it is desired to modify structure of MOS ESD protection circuit to make sure that internal chips are properly protect since chargers appear on terminal, no matter parasitic bipolar junction transistors are trigger or not.
SUMMARY OF THE INVENTION
A primary object of the invention is to provide a MOS ESD protection circuit that properly protect chips inside integrated circuits when chargers appear on terminal, no matter parasitic bipolar junction transistors are trigger or not.
A concrete object of the invention is to propose an ESD protection circuit that quality of it is not sensitively depends on fabricating process, especially not sensitively depends on parameters of fabricating process.
A further object of the invention is to provide a new way to protect chips inside integrated circuits before parasitic bipolar junction transistors of ESD protection circuit are triggered.
Another object of this invention is to propose a manufacturable MOS ESD protection circuit.
One essential embodiment of the invention is a MOS ESD protection circuit with embedded well diodes. The proposed protection circuit comprises following basic components: a well locates in a substrate; some transistors that locate in and on the well, wherein gates of transistors are located on the well, drains and sources of transistors are located in the well, and each drain is located between two adjacent sources; a pair of embedded wells that are adjacent to the well and are in contact with opposite sides of the well, herein depth of any embedded well is larger than depth of any source and depth of any drain; a guard ring that locates in the substrate, wherein guard ring surrounds well and passes through embedded wells; a pair of auxiliary doped regions that locate in the embedded well, where each auxiliary doped region and guard ring is separated by an additional isolations; some second conductive lines that couple gates with a relative ground point, these second conductive lines also couple guard ring and sources with said relative ground point; and some first conductive lines that couple drains and auxiliary doped regions with a terminal. Moreover, substrate, both well and guard ring are corresponding to a first electricity, such as positive electricity or negative electricity. And, sources, drains, embedded wells and auxiliary doped regions are corresponding to second electricity that is different to the first electricity.
REFERENCES:
patent: 5158899 (1992-10-01), Yamagata
patent: 5847429 (1998-12-01), Lien et al.
Nadav Ori
Thomas Tom
United Microelectronics Corp.
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