Ion implantation and laser anneal to create n-doped...

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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Details

C438S015000, C438S004000, C324S762010, C324S762010

Reexamination Certificate

active

06300145

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving analyzing and repair of structure in the devices.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality has been an increase in the number and complexity of the manufacturing processes, as well as an increase in the difficulty of maintaining satisfactory levels of quality control and of providing a cost-effective product using such processes.
As the manufacturing processes for semiconductor devices increase in difficulty, methods for analyzing and repairing the devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Various attributes of individual circuit elements and combinations in a semiconductor device may be tested by exciting selected areas of circuitry in the device. Testing these attributes provides an opportunity for determining such things as the integrity of the semiconductor device or, for defective devices, determining a reason for the defect. Ensuring the integrity and determining defect sources in such devices is important for maintaining proper device function, reliability, and longevity, and for improving the manufacturing process. Unfortunately, access to device circuitry for performing such analysis is difficult, and available testing methods are often impractical or otherwise inefficient. Furthermore, structure within the device is often damaged during analysis, and needs to be repaired in order to function.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. The present invention is directed to a new method for post-manufacturing analysis of a semiconductor device including a die in a semiconductor device package. The method improves access to circuitry in the die, provides a manner in which to repair damaged devices, and is particularly useful for repairing damage caused during failure analysis.
According to an example embodiment of the present invention, conductive ions are impregnated in a region of a semiconductor die having a back side opposite circuitry in a circuit side and a diode is formed. The diode is used and the semiconductor die is analyzed.
According to another example embodiment of the present invention, a semiconductor die having a back side opposite circuitry in a circuit side is analyzed. Gallium is implanted in a region in the back side, the region is annealed, and a diode is formed. A FIB is used and an electrical coupling is formed between the diode and a circuit area in the semiconductor die. The circuit area is excited via the diode, and the response of the circuit area to the excitation is analyzed.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.


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patent: 5185273 (1993-02-01), Jasper
patent: 5688715 (1997-11-01), Sexton et al.
patent: 5904489 (1999-05-01), Khosropour et al.
patent: 5930588 (1999-07-01), Paniccia
patent: 5966626 (1999-10-01), Lo et al.
patent: 6107108 (2000-08-01), Chen et al.

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