Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1998-12-29
2001-07-31
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S501000, C714S023000
Reexamination Certificate
active
06269443
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of selecting a clock frequency multiplier for a CPU.
BACKGROUND OF THE INVENTION
Many widely used microprocessors use an internal clock frequency multiplier to create a high speed clock from a lower speed system clock. For example, a Pentium® Pro processor manufactured by Intel Corporation may receive a 66 MHz clock signal from a system and multiply the system clock by 5 to create a 333 MHz clock. The processor uses the higher frequency clock signal for internal operations.
Some processors, including some processors manufactured by Intel Corporation, sample the states of various signals upon a reset of the processor to determine which multiple to use to create the internal clock. For example, a processor may have the option of multiplying the system clock by 5, or by 4, or by 3, etc. The state of various signals at reset determine which multiplier the processor will use to generate its internal clock. If the multiplier is set to create an internal clock that runs at a rate greater than that supported by the processor, the processor will fail to function properly.
FIG. 1
shows a typical prior computer system that implements a jumper scheme for selecting a clock frequency multiplier. The computer system
100
includes a processor
110
, which for this example is a Pentium® Pro processor, a system memory controller
120
, a system memory device
140
, a graphics device
130
, and a system logic device
150
. The system logic device
150
asserts a reset signal
101
to the processor upon initial power up or upon any other reset event. When the reset signal transitions from asserted to deasserted, the processor
110
samples the state of a non-maskable interrupt (NMI/STRAP) signal
102
, an interrupt (INTR/STRAP) signal
103
, an ignore numerical error (IGNE/STRAP) signal
104
, and an A20 mask (A20M/STRAP) signal
105
. The signals
102
through
105
are delivered to the processor by a multiplexor (MUX)
160
. The MUX
160
selects between the A and B inputs depending on the state of the reset signal
101
which is delivered to the MUX
160
through a reset signal delay circuit
165
. The reset circuit is typically delayed from 2 to 20 system clock periods. When the reset signal is asserted (and for a short time thereafter due to the reset delay circuit
165
), the MUX delivers the values input on its B inputs to the processor. When the reset signal is deasserted, the processor receives an A20M signal
155
, an IGNE signal
154
, and INTR signal
153
, and an NMI signal
152
by way of the A inputs on the MUX
160
.
The values presented to the B inputs of the MUX are determined by physically placing a jumper between each B input and either a logically high voltage level or a logically low voltage level. The configuration of jumpers determines the state of the signals
102
through
105
and thus the frequency multiplier used by the processor to generate its internal clock. It is also common for computer system manufacturers to use a non-volatile memory device in the place of the jumpers.
The jumper solution has a disadvantage in that if the jumpers are incorrectly configured, the processor will either fail or run too slowly. The only way to correct the problem is for a human being to change the jumper configuration. The non-volatile memory solution has the disadvantage of adding the cost of the non-volatile memory device to the cost of the system. With the non-volatile solution, if the processor fails to function correctly with the current strapping settings, the non-volatile memory must be reprogrammed. Both the jumper solution and the non-volatile memory solution incur the cost of the MUX.
SUMMARY OF THE INVENTION
A method and apparatus for automatically selecting a CPU clock frequency multiplier is disclosed. The apparatus includes a processor failure detection unit to detect that a processor has failed to operate properly following a system reset. The apparatus also includes a clock frequency multiplier indicator circuit to indicate which clock frequency multiplier strapping is to be provided to the processor. The clock frequency multiplier indicator circuit indicates a different strapping if the processor failure detection unit detects that the processor failed to operate properly following a system reset.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5371417 (1994-12-01), Mirov et al.
patent: 5852728 (1998-12-01), Matsuda et al.
patent: 6107846 (2000-08-01), Shinmori
Bains Kuljit S.
Poisner David I.
Heckler Thomas M.
Intel Corporation
Lin Isaac
LandOfFree
Method and apparatus for automatically selecting CPU clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for automatically selecting CPU clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for automatically selecting CPU clock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2556435