Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-04-27
2001-12-11
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S121000, C438S123000, C438S126000, C438S108000, C257S675000, C257S737000, C257S787000, C029S832000, C029S840000
Reexamination Certificate
active
06329228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a construction of a semiconductor device comprising a semiconductor integrated circuit chip mounted on a wiring board and sealed with a resin, and a method of fabricating the same, more particularly to a construction of a plastic ball grid array having a resin sealing body on the front surface of the wiring board on which the semiconductor integrated circuit chip is mounted and solder ball terminals on the back surface thereof, and a method of fabricating the same.
2. Description of the Related Art
The semiconductor integrated circuit chip is generally used when it is sealed by a package, which has functions of electrically connecting each electrode and a mother board, protecting a circuit and radiating heat.
A plastic ball grid array which is a type of this package (hereinafter referred to as PBGA) is a surface multi-terminal package having a construction such that a semiconductor integrated circuit chip is mounted on the front surface of a wiring board formed mainly of a resin composite, solder ball terminals provided in a matrix on the entire back surface of the wiring board for connecting the wiring board and a mother board, and the periphery of the semiconductor integrated circuit chip is sealed with a resin.
The PBGA structure is advantageous compared with other packages in respect of miniaturization of the package, electric properties and mounting yield and so forth, and it is particularly employed in the fields of personal computers and cellular communication equipment.
A semiconductor device having a conventional PBGA structure is described with reference to FIG.
17
.
FIG. 17
is a schematic sectional view of the conventional semiconductor device.
A semiconductor device
22
comprises a wiring board
1
having a core formed of a substantially square resin board
13
, and a semiconductor integrated circuit chip
2
, a plurality of connection wires
7
for electrically connecting each electrode of the semiconductor integrated circuit chip
2
with the wiring board
1
, and a plurality of substrate electrodes
3
which are respectively mounted on the wiring board
1
.
The semiconductor device
22
has a die pad
4
for fixing the semiconductor integrated circuit chip
2
onto the front surface of the wiring board
1
using a die bond adhesive
6
.
Formed on the front surface of the wiring board
1
are a resin insulating film
5
for covering and protecting each substrate electrode
3
and wirings, and a resin sealing body
28
for sealing and protecting the semiconductor integrated circuit chip
2
, the connection wires
7
and the substrate electrodes
3
.
Pad electrodes
9
are formed on the back surface of the wiring board
1
corresponding to the substrate electrodes
3
, and solder ball terminals
10
for electrically connecting the wiring board
1
and a mother board, not shown, are soldered onto the pad electrodes
9
.
The resin insulating film S is also provided on the back surface of the wiring board
1
for covering and protecting the pad electrodes
9
and the wirings.
The semiconductor device
22
has through holes
11
for electrically connecting each substrate electrode
3
on the front surface of the wiring board
1
and each pad electrode
9
on the back surface of the wiring board
1
.
There are provided a plurality of substrate electrodes
3
, through holes
11
, pad electrodes
9
and solder ball terminals
10
although only two pieces are illustrated in
FIG. 17
, for illustration reasons.
A method of fabricating the semiconductor device having the conventional PBGA structure is now described.
The wiring board
1
on which the semiconductor integrated circuit chips
2
are mounted is formed with the resin board
13
as the core which is substantially square and has a thickness of about 0.4 mm.
As a material of the resin board
13
, a glass fiber reinforced epoxy resin or a glass fiber reinforced BT resin is employed both having an excellent insulating property.
A plurality of semiconductor integrated circuit chips
2
can be mounted on the common wiring board
1
in given intervals as shown in
FIG. 18
, so that the semiconductor integrated circuit chips
2
having the PBGA structure can be fabricated at a time in order to reduce the fabricating time and improve fabricating yield.
First, copper foils each having a thickness of about 18 &mgr;m are stuck to the front and back surfaces of the resin board
13
serving as the core of the wiring board
1
as shown in FIG.
17
.
Then, cylindrical holes for providing the through holes
11
are provided on the resin board
13
having the copper foil thereon by perforating means such as a cutting drill.
Thereafter, electroless copper plating is applied to the entire surface of the perforated resin board
13
including the inner peripheral surfaces of the cylindrical holes provided on the resin board
13
, thereby forming a copper plating layer so that the through holes
11
for electrically connecting the copper foils formed on the front and back surface of the resin board
13
, and the copper film formed of an electric plating layer.
The copper films formed on the front and back surfaces of the resin board
13
on which the through holes
11
are provided are patterned by an etching treatment using an etching prevention film which is a photoresist, and etchant.
The substrate electrodes
3
, the die pad
4
and a wiring pattern, not shown are provided on the front surface of the resin board
13
and the pad electrodes
9
and another wiring pattern, not shown are provided on the back surface of the resin board
13
by the etching treatment.
As mentioned above, the wiring board
1
is designed to mount the plurality of semiconductor integrated circuit chips
2
.
Accordingly, the number of die pads
4
provided corresponds to the number of semiconductor integrated circuit chips
2
to be mounted on the front surface of the one piece of resin board
13
. Further, a plurality of substrate electrodes
3
are arranged along each end of the substantially square to surround the respective die pads
4
.
Further, the number of pad electrodes
9
formed on the back surface of the resin board
13
corresponds to the number of terminals of the semiconductor integrated circuit chips
2
and the number of semiconductor integrated circuit chips
2
to be mounted. The pad electrodes
9
per one semiconductor integrated circuit chip
2
are arranged in a matrix on the back surface of the resin board
13
in given intervals.
Thereafter, the resin insulating film
5
is provided on the front surface of the resin board
13
so as to cover the wiring pattern and the openings of the through holes
11
while the substrate electrodes
3
and the die pads
4
are exposed. Further, the resin insulating film
5
is also provided on the back surface of the resin board
13
so as to cover the wiring pattern and the openings of the through holes
11
while the pad electrodes
9
are exposed.
As a material of the resin insulating film
5
, an acrylic resin or epoxy resin respectively having an excellent insulating property is used.
The wiring board
1
shown in
FIG. 17
is completed in the foregoing processes.
Then, as shown in
FIG. 18
, a plurality of semiconductor integrated circuit chips
2
are bonded onto the die pad
4
shown in
FIG. 17
using the die bond adhesive
6
. As a material of the die bond adhesive
6
, a thermosetting resin adhesive is used.
Thereafter, each electrode of the plurality of semiconductor integrated circuit chips
2
mounted on the wiring board
1
as shown in FIG.
18
and each substrate electrode
3
provided around the semiconductor integrated circuit chips
2
as shown in
FIG. 17
are electrically connected to one another by the connection wires
7
. As a material of the connection wires
7
, an aluminum wire or a gold wire is used.
A flow stop
14
is provided substantially square along the outer periphery of the wiring board
1
as shown in
FIG. 18
to form an outer shape of the resin sealing body for sealing the plural
Armstrong Westerman Hattori McLeland & Naughton LLP
Citizen Watch Co. Ltd.
Elms Richard
Luu Pho M.
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