Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-27
2001-12-11
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S315000, C257S316000, C257S317000, C257S321000, C257S390000, C438S264000
Reexamination Certificate
active
06329687
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor memory devices and more particularly to a two bit flash memory device.
Semiconductor based memory devices largely comprise Random Access Memories (RAM) and Read Only Memories (ROM). RAM is referred to as volatile memory, in that when supply voltage is removed, data is destroyed with the passage of time. ROM devices, including Programmable ROM (PROM), Erasable PROM (EPROM), and Electrically EPROM (EEPROM). Numerous EEPROM cells and flash memory cells can be simultaneously erased, and are characterized by a stacked gate structure comprising a floating gate and a control gate.
Flash memory cells can be grouped into NAND type and NOR type circuits. NAND flash memory cells have n cell transistors connected in series and are connected in parallel between bit lines and ground lines. NAND flash memory cells are useful in large scale integration. NOR flash memory cells include cell transistors that are connected in parallel between bit lines and ground lines. NOR flash memory cells provide high-speed operation.
Conventional flash memory cells operate as follows. A cell is programmed by applying a relatively high voltage (Vg), for example 12 volts, to a control gate and a moderately high voltage (Vd), for example 9 volts, is applied to the drain in order to produce “hot electrons”, that is high energy electrons, in the channel near the drain. The hot electrons accelerate across the tunnel oxide and into the floating gate. The hot electrons are trapped in the floating gate that is surrounded by an insulator. A gate is a “floating gate” when it is located between a control gate and a substrate, and is not connected to a wordline, bitline, or other line. The insulators can include the interpoly dielectric and the tunnel oxide. The trapped electrons cause the threshold voltage of the cell to increase by approximately 3 to 5 volts. The cell is programmed by this change in the threshold voltage and the channel conductance of the cell created by the trapped electrons. The floating gate can hold its charge almost indefinitely, even after power is turned off to the memory cell. Such a memory cell is called “nonvolatile”. The memory cell can be a flash EEPROM, and EEPROM, or other programmable nonvolatile memory.
The memory cell is read by applying a predetermined voltage (Vg) to the control gate. Vg is greater than the threshold voltage of an unprogrammed cell and less than the threshold voltage of a programmed cell. If the cell conducts, then the cell has not been programmed. The cell is said to be at a first lower logic state, for example “zero”. Likewise, if the cell does not conduct, then the cell has been programmed. The cell is at a second higher logic state, for example “one”.
The flash memory cell is erased by applying a relatively high voltage (Vs), for example 12 volts, to the source, ground (Vg=0) is applied to the control gate, and the drain floats. A strong electric field is developed across the tunnel oxide between the floating gate and the source region. Some electrons are trapped in the floating gate flow toward the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of tunneling through the tunnel oxide. The electrons are removed from the floating gate, and the cell is erased.
The memory cell is activated by applying a voltage to the control gate. When the control gate is coupled to a voltage level, the two bit memory cell is enabled. The memory cell is in a non-conducting state when not enabled.
BRIEF SUMMARY OF THE INVENTION
This invention relates to the method of fabricating a two bit semi-conductor device and the resulting apparatus.
The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material forms sources/drains. the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers. Finally, a control gate layer is formed over the gate dielectric layer.
A two bit semi-conductor memory device includes a substrate, a dielectric layer, a center dielectric region, a plurality of spacer regions, a gate dielectric layer, and a control gate layer. The semiconductor substrate includes a first conductive materials and regions of a second conductive material. The second conductive material are source/drain regions. The dielectric layer with a first thickness covers the semiconductor substrate. The center dielectric region with a second thickness covers the substrate. The second thickness is greater than the first thickness. The plurality of spacer regions are located near the center dielectric region. Each spacer region is separated from the others by the center dielectric region and each spacer region is substantially the thickness of the difference between the second and first thickness. The gate dielectric layer covers the plurality of polysilicon layers and the center dielectric layer. Finally, a control gate layer covers the gate dielectric layer.
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patent: 5768192 (1998-06-01), Eitan
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patent: 5943267 (1999-08-01), Sekariapuram et al.
patent: 5943572 (1999-08-01), Krautschneider
patent: WO 990/07000 (1999-02-01), None
Higashitani Masaaki
Huster Carl Robert
Sobek Daniel
Thurgate Timothy
Abraham Fetsum
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Andujar Leonardo
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