Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Utility Patent
1999-11-23
2001-01-02
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257S522000
Utility Patent
active
06169017
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a metal-oxide-semiconductor (MOS) with an increased gate contact area.
2. Description of the Related Art
In deep sub-micron integrated circuit technology, the line width, the contact area and the contact depth are continuously being reduced. To effectively raise the quality of a device, to decrease the resistance and to reduce the RC delay time due to a high resistance and capacitance, the fabrication of the MOS transistor tends to employ a silicide layer to reduce the contact resistance at the gate and the source/drain region. Since the fabrication of a silicide layer does not require the photolithography process, it is thus known as the self-aligned silicide process. A commonly known silicide includes titanium silicide (TiSi
x
). Since titanium silicide has a low resistance and is more easily controlled during the fabrication process, titanium silicide becomes popular in the fabrication of a semiconductor device.
The conventional self-aligned silicide fabrication process includes providing a semiconductor substrate having a shallow trench structure. A polysilicon gate is formed on the substrate, wherein the gate comprises a spacer. A source/drain region is also formed in the substrate on both sides of the gate.
Thereafter, a layer of titanium is deposited on the semiconductor substrate, covering the gate and the surface of the source/drain region. A two staged rapid thermal process (RTP) is conducted for titanium to react with the silicon on the surface of the source/drain region and the gate to form a titanium silicide layer on the surface of the gate and the source/drain region. The unreacted titanium layer is then removed by wet etching to complete the self-aligned silicide manufacturing process.
The titanium silicide comprises the high resistance metastable C49 phase titanium silicide (C49-TiSi
2
) and the low resistance, thermodynamically stable C54 phase titanium silicide (C54-TiSi
2
). The first stage of the rapid thermal process results in the titanium silicide layer (TiSi
2
) comprising a major component of the C49 phase and a minor component of the C54 phase. Thereafter, the unreacted titanium is removed. In the second stage of the rapid thermal process, the temperature is further increased to rapidly anneal in-situ, transforming the titanium silicide layer from the high resistance C49 phase titanium silicide to the low resistance C54 phase titanium silicide.
The resistance of the C49 phase titanium silicide is higher and its formation temperature is lower. On the other hand, the resistance of the C54 titanium silicide is lower and its formation temperature is higher. In general, the titanium silicide is transformed from the high resistance C49 phase to the low resistance C54 phase via a rapid thermal process. In order for the metal layer and silicon to react to form a silicide layer with a substantial thickness and a more uniform quality, it is necessary to increase the temperature and the duration for the thermal process
Along with the size reduction of the polysilicon gate, the formation temperature for the C54 phase titanium silicide is increased due to the narrow line effect. The narrow line effect refers to the relationship between the linewidth and the phase transformation temperature. As the linewidth decreases, the phase transformation temperature for the titanium silicide to transform from the high resistance C49 phase to the low resistance C54 phase increases. As the temperature for the RTP process is increased to form the C54 titanium silicide, the quality of the titanium silicide becomes unstable and is not suitable for use in a small-dimension device. In addition, the higher reaction temperature is difficult to control, and lateral growth of silicon from the source/drain region to the spacer is likely to occur. As a result, as the device integration increases and the device dimension decreases, bridging is likely to occur on the side of the gate. To avoid the occurrence of bridging, the reaction temperature cannot be raised. Consequently, a higher resistance results at the polysilicon gate due to the narrow line effect and the difficulty of phase transformation.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a method to increase the gate contact area, wherein a side-wing layer is formed on both sides of the gate to increase the area for a silicide formation and to lower the gate contact resistance. The narrow line effect is thus prevented. An air spacer is further formed under the side-wing layer to reduce the parasitic capacitance between the gate and the source/drain region
The current invention provides a fabrication method for a semiconductor device in which the gate contact area is increased. The method is applicable on a substrate comprising isolation structures. The method includes forming a gate structure on the silicon substrate. A conformal sacrificial layer is formed on the silicon substrate and on the gate structure. A light doping is conducted to form a lightly doped source/drain region at both sides of the gate in the silicon substrate. A first spacer is then formed on the sidewall of the gate structure. A heavy doping is further performed on both sides of the gate structure in the substrate, using the spacer as mask, to form the heavily doped source/drain region. Thereafter, a second sacrificial layer is formed covering the silicon substrate, followed by partially removing the second sacrificial layer, the first spacer and the first sacrificial layer until the surface of the second sacrificial layer is lower than the top of the gate by a certain thickness. A conformal polysilicon layer is then formed, covering the silicon substrate. After this, a second spacer is formed on the sidewall of the gate on the conformal polysilicon layer. The portion of the polysilicon layer that is not covered by the second spacer is removed to from a sidewing polysilicon layer at both sides of the gate. The second spacer, the second sacrificial layer, the first spacer and the first sacrificial layer are removed. Subsequently, a metal salicidation process is conducted on the gate, the side-wing polysilicon layer and the surface of the source/drain region to form a silicide layer. An insulation layer is then formed on the silicon substrate covering the side-wing polysilicon layer. An air spacer is thus formed under the polysilicon side-wing layer.
The present invention provides a fabrication method for a semiconductor device, in which a side-wing layer is formed on both sides of the gate to increase the gate area for silicidation and to avoid the narrow line effect. In addition, an air spacer is formed under the side-wing layer to reduce the parasitic capacitance between the gate and the source/drain region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5869379 (1999-02-01), Gardner et al.
patent: 6015746 (2000-01-01), Yeh et al.
patent: 6104077 (2000-08-01), Gardner et al.
Elms Richard
Huang Jiawei
J.C. Patents
United Silicon Incorporated
Wilson Christian D.
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