Computer memory controller with self refresh performed...

Details Computer memory controller with self refresh performed... Computer memory controller with self refresh performed...

1998-06-19

2001-10-30

Gossage, Glenn (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000, C711S167000

Reexamination Certificate

active

06311250

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a computer memory controller, and more particularly to a computer memory controller for a memory in the form of a dynamic random access memory structure that has a battery back-up function.
BACKGROUND OF THE INVENTION
Memories are widely well known which have a memory back-up function to maintain information using a battery in case of a power failure. If the memory is a DRAM, it is essential, in the memory back-up control, for the DRAM to a refresh operation.
Usually, a refresh operation of a DRAM may be performed according to a row address strobe (RAS) only refresh (ROR) method or a column address strobe (CAS) before RAS (CBR) method or a self-refresh method. However, the CBR method is usually employed in performing a refresh operation for memory back-up control in case of power failure. The ROR method may be used in performing a refresh operation for memory back-up control in case of power failure. However, this method requires setting of fresh addresses each time upon performing refresh operation. Further, the refresh addresses must be handed over during a shift from memory back-up operation to a usual or normal operation or vice versa causing increased complexity of memory back-up control. This explains why the ROR method has not been widely employed.
Conventionally, few computer memory controllers are designed to provide a self-refresh function of a DRAM operable to perform a refresh operation when a memory back-up operation is needed. This is because DRAMs with a self-refresh function are not yet popular in the market and thus the number of such DRAMs is very small.
Accordingly, it is the conventional practice to use the CBR method in performing a refresh operation upon memory back-up operation using a battery as shown, for example, in JP-A 3-237678, which is illustrated in FIG.
4
. In
FIG. 4
, the reference numeral
44
indicates a clock generator, which generates a refresh RAS signal (RRS signal)
48
and a refresh clock source signal (RFCK signal)
46
. The reference numeral
45
indicates a refresh switch. A power failure signal (PF signal)
43
is used as an input to the refresh switch
45
for the refresh switch
45
to output a switch signal
47
. The level of the PF signal
43
determines the level of the switch signal
47
. RAS signal
41
and RFCK signal
46
are also used as inputs to the refresh switch
45
, causing the refresh switch
45
to generate a refresh CAS signal (RCS signal)
49
. The reference numerals
4
A and
4
B designate a RAS selector and a CAS selector, respectively. RAS signal
41
and RRS signal
48
are used as inputs to the RAS selector
4
A. CAS signal
42
and RCS signal
49
are used as inputs to the CAS selector
4
B. In response to the refresh switch signal
47
, the RAS selector
4
A selects one of its inputs for output to a DRAM
4
C, and the CAS selector
4
B selects one of its inputs for output to the DRAM
4
C. This accomplishes a refresh operation mode necessary for assuring contents stored in the memory are maintained.
The timing chart of
FIG. 5
illustrates operation of the conventional example shown in FIG.
4
. During usual operation mode, RAS signal
41
and CAS signal
42
are fed to DRAM
4
C. As illustrated in
FIG. 5
, the ROR method is used for refresh operation during normal operation mode, while the CBR method is used for refresh operation during back-up operation.
According to the conventional computer controller, the CBR method, which is employed for refresh operation during back-up mode operation, consumes a great amount of electricity out of a limited amount of electric power battery supply. Thus, the time period that the memory can be backed up is reduced. This is because the power consumption by DRAM during refresh operation according to a CBR method is as great as that during a usual operation.
To remedy this problem, it may be an alternative to employ a self-refresh operation of DRAM by redesigning a computer memory controller. However, the computer memory controller as redesigned poses a potential problem that it cannot provide a memory back-up function when a DRAM without a self-refresh function is installed. As mentioned before, the number of DRAMs with self-refresh function is limited in the market and most of the DRAMs available in the market are not provided with a self-refresh function, which requires a CBR method for refresh operation.
An object of the present invention is to provide a computer memory controller, which is operable to reduce power consumption during memory back-up operation within a DRAM having memory back-up function.
A further object of the present invention is to provide a computer memory controller, which is operable to select a refresh operation during a memory back-up mode in the case that DRAM is installed that is not provided with a special refresh function, such as a self-refresh function, needed for reducing power consumption.
SUMMARY OF THE INVENTION
A computer memory controller according to the present invention is intended for a memory in the form of a DRAM having a memory back-up function in case of power failure. The computer memory controller is operable to perform refresh operation, during memory back-up operation mode, in accordance with a self-refresh method.
Specifically, the computer memory controller comprises a DRAM timing control section, which generates a timing signal suitable for a self-refresh function of a DRAM and provides the timing signal to the DRAM, and a back-up control section, which detects a memory back-up state and outputs the detected result to the DRAM timing control section. The computer memory controller also comprises a DRAM identification (ID) mode register, which can identify the fact that a DRAM without a self-refresh function is in use. The DRAM timing control section is operable in response to the state of the mode register to provide a refresh operation suitable for the DRAM that is in use.


REFERENCES:
patent: 4977537 (1990-12-01), Dias et al.
patent: 5365487 (1994-11-01), Patel et al.
patent: 5590082 (1996-12-01), Abe
patent: 5594699 (1997-01-01), Nomura et al.
patent: 5634106 (1997-05-01), Yaezawa et al.
patent: 5636171 (1997-06-01), Yoo et al.
patent: 5640357 (1997-06-01), Kakimi
patent: 30 03 524 (1980-08-01), None
patent: 3-237678 (1991-10-01), None
patent: 6-208503 (1994-07-01), None
patent: 7-334432 (1995-12-01), None
patent: 97/17647 (1997-05-01), None

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