Trench DRAM cells with self-aligned field plate

Details Trench DRAM cells with self-aligned field plate Trench DRAM cells with self-aligned field plate

1998-07-27

2001-07-03

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S301000, C257S303000, C257S310000, C257S411000

Reexamination Certificate

active

06255682

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically, to a structure of a Dynamic Random Access Memory (DRAM) cell. Still more particularly, the present invention relates to a trench DRAM cell with self-aligned field plate.
BACKGROUND
In recent years, the development of semiconductor devices has a trend in the direction of increased packing density on a chip. Thus, the development of a high density memory cell is being carried out. Typically, the DRAM cells are applied to store data for a computer. These semiconductor memory devices have large capacitance for the reading out and storing of information. Dynamic Random Access Memories are so named because their cells can retain information only temporarily, even with power continuously applied. The cells must therefore be read and refreshed at periodic intervals. A memory cell is provided for each bit stored by the DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Generally, the formation of a DRAM memory cell includes the formation of a transistor, a capacitor and contacts to external circuits.
In order to achieve high density DRAM devices, the memory cells must be scaled down in size to the sub-micrometer range. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. Therefore, the capacitance of a capacitor becomes relatively small. This decrease in storage capacitance leads to lower signal-to-noise ratios and increased errors due to alpha particle interference. Prior art approaches to overcome these problems have resulted in the development of the trench capacitor. Specifically, the trench capacitor has been given a larger aspect ratio. See “Trench Storage Node Technology for Gigabit DRAM Generations,” K. P. Muller et al., 1996, IEEE, IEDM 96-507.
The trench capacitors can upgrade the capacitance and provide better topography. However, some drawbacks are related to the trench capacitors. For example, cell leakage is a serious issue in the making of the trench capacitors. The cell leakage will degrade the retention time of the DRAM cells. The retention time is one of the important parameters of DRAM cells. One of the prior art references related to cell leakage is “Characterization of Cell Leakage of a Stacked Trench Capacitor (STT) Cell,” Takeshi Hamamoto et al., 1994 IEEE. The major cause of cell leakage is an etching process that is used to form the field plate of the capacitors. The field plate is damaged by plasma etching, which causes an amount of leakage. See “Trench Capacitor Leakage in High Density DRAM's” M. ELAHY. EDL et al., 1984, IEEE ELECTRON DEVICE LETTERS, vol. EDL. 5, No. 12, pp. 527-530. and “Scalability of a Trench Capacitor Cell for 64M bit DRAM,” B. W. Shin et al., 1989, IEEE, IEDM 89-27.
SUMMARY
In accordance with the present invention, a trench capacitor with self-aligned field plate is provided for a DRAM cell. One embodiment adapted for use in a DRAM cell will be described as follows.
The capacitor includes trenches formed in a semiconductor substrate. Recess portions are formed adjacent to the top portion of the openings of the trenches. An isolation layer is formed on the substrate and on the surface of the recess portions. A first isolation structure is formed on the substrate between the trenches. Second isolation structures are refilled into the recess portions, and the second isolation structures are raised over the isolation layer. A dielectric layer is formed in the trenches along the surface of the trenches. A first storage node is refilled into the trenches. A portion of the first storage node is formed over the first isolation structure to act as a field plate of the capacitor. A third isolation structure is formed on the field plate. The third isolation structure is formed of silicon oxide. A second storage node is formed in the substrate along the surface of the trenches.


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