Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-29
2001-07-03
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S356000, C257S361000, C257S173000
Reexamination Certificate
active
06255696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to metal-oxide-semiconductor (MOS) devices, and more particularly to electrostatic discharge (ESD) protection structures for metal-oxide-semiconductor devices.
2. Description of the Prior Art
The primary function of an ESD protection transistor is to direct ESD current away from the circuit it is protecting. Such ESD protection transistors are commonly used on microprocessors, embedded microcontrollers, application specific integrated circuits (ASIC) and other logic devices, primarily for protection of the input/output buffers. For example, in
FIG. 1
is shown a semiconductor device
10
having a NMOS output buffer, e.g., connected to an output pad
14
via line
16
, where a thick field dielectric transistor
18
, which may be a thick field oxide (TFO) transistor, is connected to line
16
to protect the output buffer
12
from ESD pulses coming from output pad
14
. A thick field oxide (TFO) transistor
18
acts as a parasitic bipolar transistor, but it must turn on before a NMOS transistor of the output buffer
12
reaches its impact ionization breakdown voltage. If the thick field oxide (TFO) transistor
18
is not designed to turn on first, then the output buffer will fail an ESD pulse or stress, at, for example, 1 kV. Typically, the level of ESD protection will vary as the fabrication process changes due to variations in the on-resistance characteristics of the output buffers. It will be appreciated that throughout the specification the ESD protection transistor being discussed may be employed between input pads and input buffers as well as at outputs, and for any other device requiring ESD protection.
A number of approaches have been used to improve ESD protection transistors. For example, silicide-blocked source and drain regions have been used to enhance ESD strength but the ESD protection is still insufficient. Another common method to ensure that ESD protection transistor turns on first is to increase the channel length of the output buffer transistors so that they are harder to turn on. However, this option results in an unacceptable increase in device area due to the simultaneous increase in device width that is necessary to maintain performance.
In input/output ESD protection metal-oxide-semiconductor (MOS) transistors, the current technology uses the ESD implant to dope the source/drain after the contact open and the doped profile is shown in FIG.
2
. The main purpose of this ESD implant is to increase the impurity concentration and to deepen the junction in the Lightly Doped Drain (LDD) region. However, this does not guarantee the reduction of the current at the surface, if without optimizing the doping profile and its ESD protection cannot be maximized.
SUMMARY OF THE INVENTION
In accordance with the present invention, an ESD protection apparatus is provided that substantially optimizes the profile of ESD implantation. The optimized profile will reduce surface current and direct ESD current to a deeper substrate, because the breakdown voltage correlates to surface current sensitivity. Moreover, the optimized profile can maximize breakdown voltage of the ESD protection transistor.
An advantage of this invention is that the breakdown voltage of the ESD transistor can be independently optimized. Additionally, the structures of the present invention can be scaled to smaller features as new technologies permit integrated circuits to be reduced further in size.
In one embodiment, a gate electrode and Lightly Doped Drain (LDD) regions are formed in and on a substrate of a semiconductor device. The ESD implantation regions using phosphorous as source ions are then formed under the Lightly Doped Drain (LDD) regions. Then spacers are formed beside gate and source/drain regions are formed next. The optimized profile is that the concentration of ESD implantation is maximum at source/drain junction depth.
REFERENCES:
patent: 5386134 (1995-01-01), Huang
patent: 5728612 (1998-03-01), Wei et al.
Anya Igwe U.
Smith Matthew
United Microelectronics Corp.
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