Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-07-01
2001-08-07
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S693000, C438S020000, C445S051000
Reexamination Certificate
active
06271139
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a polishing slurry and method for using the same in chemical-mechanical polishing, particularly in the fabrication of field emission displays.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (“CMP”) processes are widely used to remove material from the surface of a substrate in the production of a wide variety of microelectronics. In a typical CMP process, the surface to be polished is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry generally contains small, abrasive particles that abrade the surface, and chemicals that etch and/or oxidize the newly formed surface. The polishing pad is generally a planar pad made from a continuous phase matrix material such as polyurethane. Thus, when the pad and/or substrate moves with respect to the other, material is removed from the substrate surface mechanically by the abrasive particles and chemically by the etchants and/or oxidants in the slurry.
FIG. 1
schematically illustrates a polishing machine
10
, often called a planarizer, used in a conventional CMP process. The polishing machine
10
has a platen
20
, substrate carrier
30
, a polishing pad
40
, and a slurry
44
on the polishing pad. An under-pad
25
is typically attached to the upper surface
22
of platen
20
, and the polishing pad
40
is positioned on the under-pad
25
. In conventional CMP machines, a drive assembly
26
rotates the platen
20
as indicated by arrow A. In other existing CMP machines, the drive assembly
26
reciprocates the platen
20
back and forth as indicated by arrow B. The motion of the platen
20
is imparted to the pad
40
through the under-pad
25
because the polishing pad
40
frictionally engages the under-pad
25
. The substrate carrier
30
has a lower surface
32
to which a substrate
12
may be attached, or the substrate
12
may be attached to a resilient pad
34
positioned between the substrate
12
and the lower surface
32
. The substrate carrier
30
may be a weighted, free-floating carrier, or an actuator assembly
36
may be attached to carrier
30
to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional polishing machine
10
, the substrate
12
is positioned face-downward against the polishing pad
40
, and then the platen
20
and the carrier
30
move relative to one another. As the surface of the substrate
12
moves across the planarizing surface
42
of the polishing pad
40
, the polishing pad
40
and the slurry
44
polish the surface of the substrate.
CMP processes must consistently and accurately produce a uniform, planar surface. The necessity of obtaining a highly uniform, planar surface is illustrated in the manufacture of microelectronic devices manufactured on a substrate made from glass or a suitable semiconductive material (e.g., silicon) on a suitable insulating material (e.g., glass). Such microelectronic devices typically have many small components formed in multiple layers of materials. One type of microelectronic device particularly relevant to the present invention is a field emission display (“FED”).
FEDs are one type of flat panel display in use or proposed for use in computers, television sets, camcorder viewfinders, and a variety of other applications. FEDs have a baseplate with a generally planar emitter substrate juxtaposed to a faceplate.
FIG. 2
illustrates a portion of a conventional FED baseplate
20
with a conductive emitter substrate
30
, and a number of emitters
32
formed on the emitter substrate
30
. An insulator layer
40
made from a dielectric material is disposed on the emitter substrate
30
, and an extraction grid
50
made from polysilicon is disposed on the on the insulator layer
40
. A number of cavities
42
extend through the insulator layer
40
, and a number of holes
52
extend through the extraction grid
50
. The cavities
42
and the holes
52
are aligned with the emitters
32
to open the emitters
32
to the faceplate (not shown).
Referring to
FIGS. 2 and 3
, the emitters
32
are grouped into discrete emitter sets
33
in which the bases of the emitters
32
in each set are commonly connected. As shown in
FIG. 3
, for example, the emitter sets
33
are configured into rows (e.g., R
1
-R
3
) in which the individual emitter sets
33
in each row are commonly connected. Additionally, each emitter set
33
has a grid structure superjacent to the emitters that is configured into columns (e.g, C
1
-C
2
) in which the individual grid structures are commonly connected in each column. Such an arrangement allows an X-Y addressable array of grid-controlled emitter sets. The two terminals, comprising the emitters and the grids, of the three terminal cold cathode emitter structure (where the third terminal is understood to be the anode disposed on the faceplate—not shown in
FIG. 2
or
3
) are commonly connected along such rows and columns, respectively, by means of high-speed interconnects. The interconnects
60
(also shown in
FIG. 2
) are formed on top of the emitter substrate
30
and the extraction grid
50
, and they serve to electrically connect the individual grid structures forming the columns. It will be appreciated that the column and row assignments were chosen for illustrative purposes and can be exchanged.
In operation, a specific emitter set is selectively activated by producing a voltage differential between the extraction grid and the specific emitter set. A voltage differential may be selectively established between the extraction grid and a specific emitter set through corresponding drive circuitry that generates row and column signals that intersect at the location of the specific emitter set. Referring to
FIG. 3
, for example, a row signal along row R
2
of the extraction grid
50
and a column signal along a column C
1
of emitter sets
33
activates the emitter set at the intersection of row R
2
and column C
1
. The voltage differential between the extraction grid and the selectively activated emitter sets produces localized electric fields that extract electrons from the emitters in the activated emitter sets.
The display screen of the faceplate (not shown) is coated with a substantially transparent conductive material to form an anode, and the anode is coated with a cathodoluminescent layer. The anode, which is typically biased to approximately 1.0-2.0 kV, draws the extracted electrons through the extraction grid and across a vacuum gap (not shown) between the extraction grid and the cathodoluminescent layer of material. As the electrons strike the cathodoluminescent layer, light emits from the impact site and travels through the anode and the glass panel of the display screen. The emitted light from each of the areas becomes all or part of a picture element.
FIGS. 4A-4C
illustrate a prior art method for forming an FED baseplate
120
.
FIG. 4A
illustrates an initial step in which a plurality of emitters
32
are formed on an emitter substrate
30
. The emitters
32
are preferably grouped into discrete emitter sets, and the emitter sets are preferably configured into columns or rows on the emitter substrate
30
, as discussed above with respect to FIG.
3
. The emitters
32
are preferably conical-shaped protuberances that project upwardly from the emitter substrate
30
towards a faceplate (not shown). The shape of the emitters
32
, however, is not limited to conical protuberances and may be any other suitable shape. The emitter substrate
30
is typically made from conductive silicon. Alternatively, the emitters
32
may be formed from a conductive layer (not shown) that was deposited on an insulating substrate such as glass.
FIG. 4B
illustrates a subsequent stage in the method for forming the FED baseplate
120
. After the emitters
32
are formed on the emitter substrate
30
, an insulator layer
40
is deposited over the emitter substrate
30
so that the insulator layer
40
generally conforms to the contour of
Alwan James J.
Carpenter Craig M.
Dorsey & Whitney LLP
Kunemund Robert
Micro)n Technology, Inc.
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