Charge pump circuit

Details Charge pump circuit Charge pump circuit

1998-11-18

2001-09-04

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S148000, C327S157000, C331S017000

Reexamination Certificate

active

06285725

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock compensation circuit for use in synchronous DRAM (SDRAM) of high fast or RAMBUS DRAM which has received much attention recently, and more particularly, to a charge pump circuit in a delay locked loop (DLL) of a clock compensation circuit such as DLL and a phase locked loop (PLL) which outputs an inner clock by receiving an outer clock.
2. Discussion of the Related Art
A DLL device generates an inner clock by uniformly maintaining the frequency of a received outer clock and the frequency of the inner clock and controlling delay time. A PLL device generates an inner clock having different frequency from one another by converting the frequency of a received outer clock. The DLL device includes a phase detector, a charge pump circuit and a delay device. The phase detector detects phase difference between the frequency of the outer clock and the frequency of the inner clock. The charge pump circuit performs pumping operation by an output signal of the phase detector and controls a transistor of the delay device to adjust delay length of the entire cell. The delay device is controlled by the output signal of the charge pump circuit to generate the inner clock.
FIG. 1
shows a background art charge pump circuit of the DLL device. As shown in
FIG. 1
, the charge pump circuit includes a first PMOS transistor MP
1
connected between a power source voltage terminal Vcc and a first node N
1
, whose gate receives a certain bias voltage pbias; a second PMOS transistor MP
2
connected between the first node N
1
and a third node N
3
, whose gate receives a phase detector output signal pmpup; a third PMOS transistor MP
3
connected between the first node N
1
and a second node N
2
, whose gate receives a phase detector output signal /pmpup; a first NMOS diode MN
1
connected between the second node N
2
and a fourth node N
4
, whose gate is connected to a pump output terminal /pmpout; a second NMOS transistor MN
2
connected between the third node N
3
and the fourth node N
4
, whose gate is connected to the pump output terminal /pmpout; a first capacitor C
1
connected between the pump output terminal /pmpout and a ground voltage terminal Vss; a fourth NMOS diode MN
4
connected between the third node N
3
and the fourth node N
4
, whose gate is connected to the pump output terminal pmpout; a third NMOS transistor MN
3
connected between the second node N
2
and the fourth node N
4
, whose gate is connected to the pump output terminal pmpout; a second capacitor C
2
connected between the pump output terminal pmpout and the ground voltage terminal Vss; a fifth NMOS transistor MN
5
connected between the fourth node N
4
and the ground voltage terminal Vss; a sixth NMOS transistors MN
6
connected between the power source voltage terminal Vcc and the pump output terminal /pmpout, whose gate receives a DLL reset signal dll-reset; a seventh NMOS transistor MN
7
connected between the power source voltage terminal Vcc and the pump output terminal pmpout, whose gate receives the DLL reset signal dll-reset; and an eighth NMOS transistor MN
8
connected between the two pump output terminals, whose gate receives the DLL reset signal dll-reset.
The operation of the charge pump circuit will be described below.
The first PMOS transistor MP
1
is turned on by certain bias voltage so that current flows to the first node. This current is transferred to the second node or the third node through the second PMOS transistor MP
2
or the third PMOS transistor MP
3
which is selectively turned on by the phase detector output signal, and is charged to the first capacitor or the second capacitor.
For example, if the phase detector output signal pmpup is low, the second PMOS transistor MP
2
is turned on and the second capacitor is charged, so that the potential of the pump output terminal pmpout ascends. In this case, assuming that the inner clock gradually follows the outer clock, the phase of the inner clock becomes faster than the phase of the outer clock by controlling the delay device as the potential of the pump output terminal pmpout ascends.
Meanwhile, at the initial step for preparing to operate the charge pump, the two pump output terminals become high state since the charge pump is reset at the same level. Therefore, the potential of the pump output terminal pmpout depending on charge of the second capacitor ascends, so that the third NMOS transistor MN
3
is turned on and the charge of the first capacitor at the high state is discharged to the ground voltage terminal through the third NMOS transistor MN
3
.
Meanwhile, if the phase detector output signal /pmpup is low, the first capacitor is charged while the second capacitor is discharged.
In other words, if the phase of the inner clock becomes faster than the phase of the outer clock, the phase detector in the DLL device changes pumping direction of the pump to allow the inner clock to be slower than the outer clock.
If the phase of the outer clock is again faster than the phase of the inner clock, the pumping direction i, again changed so that the inner clock follows the outer clock. This operation continues to repeat. As a result, lock state is achieved.
However, the background art charge pump circuit has the following problems.
In general, performance of the DLL device is determined by the correlation between lock time and output jitter. In other words, the performance of the DLL device can be improved by reducing lock time and the size of the output jitter. The lock time means time that takes until the phase of the inner clock is identical with the phase of the outer clock, and the output jitter means movement degree of the generated inner clock.
In the background of art charge pump circuit to make the lock time fast, charge/discharge amount per hour increases by increasing the turn-on size of the first PMOS transistor MP
1
whose gate receives a certain bias voltage to flow a large amount of currents. Thus, the lock time can be reduced. However, in this case, although the lock time is reduced, a large amount of currents continues to flow after the lock and also the charge/discharge amount per hour continues to increase. This increases the size of the jitter, thereby deteriorating the performance of the DLL device.
Furthermore, since the background art charge pump circuit has no signal to indicates the lock, there exists inconvenience in interfacing with the external environment.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a charge pump circuit that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to provide a charge pump circuit which reduces lock time and the size of jitter by increasing current value before lock and reducing current value after lock, so as to improve performance of a DLL device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a charge pump circuit according to the present invention includes a lock time/jitter control means connected to a power source supply terminal and a ground terminal of the charge pump circuit, for controlling current value to allow large current value to be transferred before lock and allow small current value to be transferred after lock, and a lock time/jitter driving means for driving the lock time/jitter control means, wherein the lock time/jitter control means includes MOS transistors and the lock time/jitter control means includes a counter for receiving a phase detector output signal and a c

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