Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1998-10-02
2001-05-15
Amsbury, Wayne (Department: 2171)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C714S047300
Reexamination Certificate
active
06233680
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processing systems and more particularly to deconfiguring a processor at the boot-time of a symmetrical multi-processing (SMP) system.
BACKGROUND OF THE INVENTION
Processing systems which include memories and processors oftentimes experience failures. Sometimes these failures are so-called hard errors, from which no recovery is possible. Thereafter the device that has caused the hard error is replaced. On the other hand, oftentimes failures are repeatable or so-called soft errors, which occur intermittently and randomly. Often these soft errors are repeatable and are localized to a particular processor within the processing system. These soft errors therefore cause multiple processing system failures.
However, it is frequently difficult to obtain and maintain information in existing conventional systems about the processor soft errors. Also, in conventional processing systems, a processor with intermittent errors is typically not deallocated from the system. Clearly, what is needed is a system for determining the cause of a repeatable or soft error and a system and method for deallocating the particular processor associated with the soft error. The system must be easy to implement and cost effective, and should be easily implemented in existing systems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for deconfiguring a processor in a SMP system is disclosed. In one aspect, a processing system is disclosed that comprises multiple central processing units (CPUs), and a memory coupled to the CPUs. Each CPU includes error status registers for capturing information concerning the status of its errors. The processing system includes a service processor for gathering and analyzing status information from each CPU. The processing system also includes a nonvolatile device coupled to the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the CPUs from the service processor. The deconfiguration area also provides information for the service processor to deconfigure a CPU during the boot time of the processing system. The processing system also includes system logic to logically remove a CPU from the system.
Accordingly, through the present invention, CPU errors are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by the service processor to deallocate the defective CPU. This is accomplished through the use of error status within each CPU and system logic, and through the use of a deconfiguration area in NVRAM, which provides information directly to the service processor.
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Bossen Douglas Craig
Kitamorn Alongkorn
McLaughlin Charles Andrew
Amsbury Wayne
Carwell Robert M.
International Business Machines - Corporation
Wang Mary
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