Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or...
Reexamination Certificate
2000-01-31
2001-05-01
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Including semiconductor material other than silicon or...
C257S256000, C257S289000, C438S186000
Reexamination Certificate
active
06225680
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the fields of semiconductor technology and manufacture. More specifically, the invention relates to a silicon-carbide material-based semiconductor structure with a plurality of regions with different electrical properties. These include at least a first semiconductor region, a second semiconductor region, the surface of which includes the surface of the first semiconductor region as a first partial area, and a further semiconductor region, whose surface encompasses the surface of the second semiconductor region as a second partial area.
In the case of power semiconductor components, e.g. power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), particularly high requirements are made of the homogeneity, because many parts, referred to as cells, of these elements are frequently connected in parallel and each cell is intended to contribute the same proportion to the total current.
In the case of a configuration that is known, per se, from silicon technology, namely a vertical MOSFET cell with a so-called lateral channel region, a so-called channel length is defined by the lateral overlap of a base region over a source region of the MOSFET with an opposite conductivity type. In order to obtain a relatively low channel resistance, endeavors are made to minimize the channel length of the MOSFET cell. Furthermore, mass production of components with at least approximately identical properties requires that the channel length be substantially homogeneous across the entire wafer of semiconductor material and that it can be set in a reproducible manner from wafer to wafer.
The article “Self-Aligned 6H-SiC MOSFETs With Improved Current Drive” by J. N. Pan, J. A. Cooper, M. R. Melloch in “Electronics Letters”, Jul. 6, 1995, Vol. 31, No 14, pages 1200 and 1201 describes the structure of a lateral MOSFET using silicon carbide technology of the 6H crystal type (6H-SiC) and a method for fabricating it which is based on a method known from silicon technology. Accordingly, adjacent windows in a mask plane represent, within an epitaxially grown, p-doped 6H-SiC layer, in pairs, source and drain regions of the lateral MOSFET which are in each case n-doped by implantated nitrogen ions. However, since distinctly higher temperatures are required for SiC in comparison with silicon for annealing the lattice damage produced during the implantation and for activating the implanted dopants (1200° C.-1500° C. for SiC; 750° C.-800° C. for Si), the use of the MOS system as masking is problematic. In order not to damage the MOS system, heat treatment can be effected only at temperatures of up to a maximum of 1200° C. Consequently, it is not possible to activate the acceptor ions. The channel length is set by way of the distance between the windows in the mask, and the gate oxide and the gate electrode are situated in a self-aligned manner above the inversion channel. The method cannot be applied to those types of components in which a channel region is implanted, because for that purpose a p-type doping is necessary either for the source and drain or for the channel region. The maximum possible annealing temperature of 1200° C. does not suffice, however, for annealing and activating the acceptor ions.
The article “4H-Silicon Carbide Power Switching Devices” by J. W. Palmour, et al. in “Technical digest of International conference on SiC and related materials”, Kyoto, Japan, 1995, pages 813-16 describes a non-planar UMOS structure in silicon carbide of the 4H crystal type. The source regions are produced by the implantation of donor ions into an epitaxially grown p-doped SiC layer. By means of reactive ion etching (RIE), aligned in each case with the center of the source regions, a U-shaped trench is opened in the surface of the semiconductor structure. The trenches each extend down into the n-doped SiC layer arranged under the p-doped SiC layer and successively accommodate the gate oxide and the gate electrode. The channel length is defined by the thickness, of the p-doped SiC layer, which remains in the vertical direction between the source region and the n-doped SiC layer. Just a single implantation step is provided in that process as well. The channel length is controlled by way of the penetration depth of the nitrogen ions and the thickness of the p-doped SiC layer.
In the case of the SiC semiconductor structures which are known as DI
2
-MOSFETs (see, for example, “IEEE Electron Device Letters”, by J. N. Shenoy et al., Vol 18, No 3, March 1997, pages 93-95) and have a plurality of mutually enclosing surface regions, the distances between the edges of the mutually enclosing surface regions—the distances defining the lateral channel lengths—are comparatively non-uniform when considered over the entire periphery of a respective partial region. In other words, the distances between adjacent edges fluctuate by an order of magnitude of distinctly more than 50 nm. It is then shown, however, that, for instance in the case of many partial regions of a corresponding structure being connected in parallel, the partial regions are locally loaded to different extents in electrical terms and thus non-uniformly in thermal terms. Consequently, the advantages of a high loading capability in the application of SiC material are correspondingly reduced because of the requirement for avoiding the overloading of individual partial regions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a silicon-carbide based semiconductor structure with several electrically distinct partial regions, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which ensures a high loading capability particularly in the case in which many partial regions are connected in parallel.
With the foregoing and other objects in view there is provided, in accordance with the invention, an SiC semiconductor structure, comprising:
a first semiconductor region having a surface area;
a second semiconductor region having a surface area encompassing the surface of the first semiconductor region as a first partial area;
a further semiconductor region having a surface area encompassing the surface of the second semiconductor region as a second partial area;
the first partial area having an edge with a predetermined contour; and
the second partial area having an edge with a contour determined by the predetermined contour of the edge of the first partial area such that a plurality of equi-radial circles imaginarily described around each point of the edge of the first partial area and assigned a common outer envelope defines the contour of an imaginary exact edge of the second partial area, whereby an actual edge of the second partial area is spaced at most ±10 nm from the exact edge.
In accordance with an added feature of the invention, the first, second, and further semiconductor regions have mutually different electrical properties.
In other words, the object of the invention is satisfied in that the contour of the edge of the first partial area is predetermined, and that the contour of the edge of the second partial area is determined by the contour of the edge of the first partial area to the effect that a circle having the same radius is imaginarily described around each point of the edge of the first partial area and all the circles are assigned a common outer envelope which defines the contour of an imaginary exact edge of the second partial area, the actual edge of the second partial area being at a distance at most of ±10 nm from the exact edge.
This is based on the fact that the lateral distances between the edges of mutually enclosing partial regions determine the electrical properties of the semiconductor structure. Only lateral distances with very close tolerances advantageously allow a generally uniform, high electrical and/or thermal loading of the so-called lateral channels which run between the edges, where the corresponding tolerances of the channel lengths ar
Peters Dethard
Schorner Reinhold
Greenberg Laurence A.
Lee Eddie C.
Lerner Herbert L.
SiCED Electronics Development GmbH & Co. KG
Stemer Werner H.
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