Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-10-21
2001-03-06
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S301000
Reexamination Certificate
active
06198151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a transistor and a capacitor formed on the major surface of a semiconductor substrate, a semiconductor integrated circuit device formed by integrating such semiconductor devices, and a method of manufacturing same.
2. Description of the Related Art
In an integrated circuit formed by integrating memory cells including Metal Oxide Semiconductor (MOS) transistors and capacitors on the major surface of a semiconductor substrate, the integration density can be increased by reducing an area occupied by the capacitors on the major surface of the semiconductor device, so that a large-scale integrated circuit can be realized.
As a capacitor used such a memory cell, a stacked capacitor formed to extend upward from the major surface of a semiconductor substrate, or a trench capacitor formed by forming a trench in the major surface is known. In a memory cell using such a capacitor, a unit memory cell is generally constituted as a one-transistor memory cell including one MOS transistor and one capacitor.
According to the one-transistor memory cell, since the number of functional circuit elements constituting a unit memory cell is small, an area occupied by the unit memory cell is small. For this reason, the number of memory cells per a unit area, i.e., an integration density in a storage element integrated device can be sufficiently increased.
However, in recent years, a power supply voltage tends to decrease with development of micropatterning technique, thereby compressing a signal amplitude. An operation of reliably reading an information signal from a memory cell cannot be easily performed.
For example, in a dynamic random access memory (DRAM), a signal from a memory cell at a read address is transmitted to one of a pair of bit lines, and the other of the pair of bit lines receives a signal from a dummy cell, so that a potential difference between the pair of bit lines is detected as information by using a gated flip-flop as a sensing circuit.
In this sensing operation, in a storage circuit using the one-transistor memory cell, an amount of a setting error of a signal potential of the dummy cell or an amount of a variation in power supply voltage is a part which cannot be used as a dead zone of the power supply potential. For this reason, when the power supply voltage is lowered with development of micropatterning technique, a stable storing operation cannot be performed.
In order to avoid this problem, for example, as described in Japanese Patent Application No. 59-136110 (Japanese Patent Application Laid-Open No. 61-16099), Japanese Patent Application No. 60-81829 (Japanese Patent Application Laid-Open No. 61-240497), Japanese Patent Application No. 60-204087 (Japanese Patent Application Laid-Open No. 62-65295), a two-transistor memory cell structure in which one memory cell includes two transistors and one capacitor to complementarily transmit the same information signal to both of a pair of bit lines is proposed.
However, in the two-transistor memory cell constituted by two MOS transistors and one capacitor, a space occupied by each memory cell increases. For this reason, the two-transistor memory cell structure cannot be easily realized without decreasing an integration density, i.e., a memorizing density. Therefore, an increase in integration density of storage elements and a stable operation performed under the state wherein the power supply voltage is lowered with application of micropatterning technique can not be made compatible.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above problem, and has as its object to provide a semiconductor device, semiconductor integrated circuit device, and method of manufacturing same which can be integrated at a high integration density and can be stably operated even if a power supply voltage tends to be lowered.
A semiconductor device according to the present invention comprises: a first conductive film selectively formed above a semiconductor layer and an insulating film is lying between them; a pair of first impurity regions formed in the semiconductor layer beside of the first conductive film; a trench formed in the semiconductor layer beneath the first conductive film; a dielectric film formed to cover the inner surface of the trench; and a second conductive film buried inside the trench having the inner surface covered with the dielectric film.
In this semiconductor device according to the present invention, the trench is formed in the semiconductor layer beneath the first conductive film functioning as a gate electrode that is a constituent element of a MOS transistor, and the dielectric film and the second conductive film as constituent elements of the capacitor are formed in the trench. Since this structure is used, an area occupied by a unit element decreases. For this reason, by applying the semiconductor device of the present invention, a semiconductor integrated circuit having a high density can be realized.
The semiconductor device according the present invention may be applied to the two-transistor memory cells, and the source and drain of the MOS transistors are connected to a pair of information lines (i.e., a pair of bit lines to which complementary information is given), respectively, to supply a complementary signal to a sense circuit. In this case, storing and reading operations are reliably performed, and a stable operation can be performed at a low power supply voltage.
The semiconductor device according to the present invention may comprise a second impurity region formed in the semiconductor layer at side-wall portions on both sides of the trench. The semiconductor layer may comprise a first semiconductor layer of a reverse conductivity type to the conductivity type of the first impurity region, and a second semiconductor layer formed on the first semiconductor layer, and the trench is formed in the second semiconductor layer such that the bottom portion of the trench reaches the first semiconductor layer. The first semiconductor layer may comprise a monocrystalline silicon substrate containing a higher-concentration impurity of one conductivity type, and the second semiconductor layer may comprise a silicon epitaxial layer containing a lower-concentration impurity of the one conductivity type. The dielectric film may comprise a nitride film, or may comprise a three-layered structure including an oxide film, a nitride film, and an another oxide film, or may comprise a ferroelectric film. The second conductive film may comprise a polycrystalline silicon film containing an impurity.
A semiconductor integrated circuit device according to the present invention comprises: a plurality of semiconductor layers of one conductivity type formed on one major surface of a substrate to be insulated from each other; a MOS transistor formed on the semiconductor layer; and a memory capacitor formed by using a first trench formed in the semiconductor layer beneath a gate electrode of the MOS transistor.
In this semiconductor integrated circuit device, the upper end of the first trench may oppose the gate electrode of the MOS transistor through an insulating film, and the lower end of the first trench may reach the substrate. The memory capacitor may comprise a dielectric film formed inside the first trench, and a conductor surrounded with the dielectric film and held at a floating potential. The memory capacitor may further comprise a conductive region which is formed at both side-wall portions of the first trench through the dielectric film to be capacitively coupled with the conductor. In this case, the conductive region may be formed by doping an impurity of a reverse conductivity type to the conductivity type of the semiconductor layer into the semiconductor layer. The semiconductor layers may be formed almost parallel to each other in one direction to be insulated from each other on the substrate, and the MOS transistors and the memory capacitors may be formed to be align
Holland & Hart LLP
Nippon Steel Semiconductor Corp.
Prenty Mark V.
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