Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-06-28
2001-07-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06263460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of integrated circuits and more particularly to the manufacture of microcontrollers having “on-chip” memory devices.
2. Description of Related Art
A typical computer system includes a microprocessor secured within a semiconductor device package and connected via signal lines to several separately-packaged support circuits. These support circuits typically include one or more memory devices and circuits which perform an interface function between the microprocessor and the one or more memory devices. A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Various microcontrollers include memory interface circuits and one or more memory devices along with a microprocessor core on the same chip. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
FIG. 1
is a block diagram of an exemplary microcontroller
10
including a microcontroller core
12
coupled to an “on-chip” memory device
14
and to several input/output (I/O) pads
16
. During manufacture of microcontroller
10
, signal lines to be connected to external devices are terminated at I/O pads
16
. I/O pads
16
are flat metal contact regions located upon an exposed surface of the chip. Following manufacture, microcontroller
10
is typically secured within a protective semiconductor device package. Each I/O pad is then connected to a terminal (i.e., pin) of the device package by a signal line (i.e., a wire).
Microcontroller core
12
includes a microprocessor core
18
and memory interface circuitry
20
. Microprocessor core
18
is configured to execute microprocessor instructions, for example instructions from an x86 instruction set. Memory interface circuitry
20
generates control signals which enable the storing of data within and the retrieving of data from memory device
14
as well as any other memory devices connected to I/O pads
16
. Operations within microcontroller
10
are synchronized by a system “clock” signal.
Testing of a memory device such as memory device
14
is typically accomplished by storing data within (i.e., writing to) the memory device, subsequently retrieving the stored data (i.e., reading) the data from the memory device, and comparing the retrieved data to the stored data. If the retrieved data matches the stored data, the memory device is working properly. As on-chip memory device
14
is typically not accessible for testing via I/O pads
16
, microcontroller core
12
may be used to test the functionality of memory device
14
.
A problem arises when microcontroller core
12
is used to test memory device
14
and the testing requires that the frequency of the clock signal be altered. If the frequency of the clock signal must be increased beyond the operational capability of microcontroller core
12
in order to test the functionality of memory device
14
, microcontroller core
12
cannot be used to carry out the testing. This may occur, for example, when memory device
14
is a static random access memory (SRAM) device having memory cells with load devices, and the functionality of the load devices are to be tested.
FIGS. 2-5
will now be used to describe how a typical SRAM memory device operates, and how the functionality of the load devices is commonly tested.
FIG. 2
is a block diagram of a typical SRAM device
30
. SRAM device
30
includes a memory array
32
, a row decoder
34
, a column decoder/multiplexer
36
, and a sense amplifier
38
. Memory array
32
includes multiple memory cells, each of which store a single binary digit (i.e., bit) of data. The memory cells are typically arranged in a two-dimensional array with several rows and columns. Row decoder
34
receives m “row” address signals and produces
2
m
“row select” signals, one for each row in memory array
32
. Each column of memory cells is associated with a complementary (i.e., differential) pair of signal lines referred to as “bit” and “bit′”. Column decoder/multiplexer
36
receives n “column” address signals, selecting one of
2
n
bit and bit′ pairs to provide to sense amplifier
38
. As will be described in detail below, sense amplifier
38
senses a voltage difference between the bit and bit′ signal lines, producing a data signal having a logic level which corresponds to the voltage difference. Memory cell
40
is one of the
2
m+n
memory cells within memory array
32
.
FIG. 3
is a block diagram of a metal oxide semiconductor (MOS) memory cell
40
and sense amplifier
38
of FIG.
1
. Memory cell
40
includes a pair of cross-coupled inverters
50
a-b
, forming a latch element having a pair of nodes
52
a-b
, and a pair of pass transistors
54
a-b
. Pass transistor
54
a
selectively couples node
52
a
of the latch element to the bit signal line, and pass transistor
54
b
selectively couples node
52
b
of the latch element to the bit′ signal line. Both pass transistors
54
a
and
54
b
are controlled by the row select signal, being in a high resistance state (i.e., an “off” state) when the row select signal is deasserted, and being in a low resistance state (i.e., an “on” state) when the row select signal is asserted.
Inverter
50
a
includes an n-channel transistor
56
a
coupled between node
52
a
and a ground potential (i.e., “ground” or “V
SS
”) and a load device
58
a
coupled between node
52
a
and a positive power supply potential (i.e., “V
DD
”). Similarly, inverter
50
b
includes an n-channel transistor
56
b
coupled between node
52
b
and ground, and a load device
58
b
coupled between node
52
b
and V
DD
. Load devices
58
a-b
provide a current path from V
DD
to nodes
52
a-b
, respectively, allowing nodes
52
a-b
to be “charged” to V
DD
and to remain at V
DD
following such charging. Following charging of nodes
52
a-b
to V
DD
, current from V
DD
flowing through load devices
58
a-b
counteracts leakage currents from nodes
52
a-b
through the transistors connected thereto. Load devices
58
a-b
thus allow data stored within memory cell
40
to be retained as long as electrical power is supplied (i.e., “static” operation).
Sense amplifier
38
is used during read operations to detect a voltage difference between the bit and bit′ signal lines and to produce a data signal having a logic level which corresponds to the voltage difference. Sense amplifier
38
includes a pair of cross-coupled inverters
60
a-b
, forming a latch element having a pair of nodes
62
a-b
, a pair of pass transistors
64
a-b
, and an inverter
66
. Pass transistor
64
a
selectively couples node
62
a
of the latch element to the bit signal line, and pass transistor
64
b
selectively couples node
62
b
of the latch element to the bit′ signal line. Both pass transistors
64
a
and
64
b
are controlled by a “control” signal, being in a low resistance “on” state when the control signal is deasserted, and being in a high resistance “off” state when the control signal is asserted.
FIG. 4
is a timing diagram illustrating signal timing during the reading of a logic high or “1” from memory cell
40
having functional load devices
58
a-b
. In this case, transistor
56
a
of the latch element of memory cell
40
is “off” and node
52
a
is substantially at V
DD
, and transistor
56
b
is “on” and node
52
b
is substantially at ground potential. Prior to or as the first step in a read operation, the bit and bit′ signals lines are typically precharged to V
DD
. The row select signal is then asserted, connecting nodes
52
a
and
52
b
of the latch element of memory cell
Pinkerton, Jr. Robert I.
Spilo David A.
Advanced Micro Devices , Inc.
Amanze Emeka
Conley & Rose & Tayon P.C.
Daffer Kevin L.
De'cady Albert
LandOfFree
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