Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-19
2001-01-16
Trinh, Michael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S903000, C365S156000
Reexamination Certificate
active
06175138
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular, to a semiconductor memory device consisting of an SRAM (Static Random Access Memory) and a method of manufacturing the same.
A memory, which is well known as an LSI (Large Scale Integrated Circuit), is generally classified into an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory). Most of these memories are composed of MOS (Metal Oxide Semiconductor) transistors because the MOS transistor is superior in integration.
In this event, the SRAM has rapid operation speed in comparison with the DRAM. Consequently, the SRAM is widely used, for example, as a cache memory in which a high-speed operation is particularly required.
The SRAM is basically composed of a flip-flop circuit. In such a flip-flop circuit, an input electrode and an output electrode are connected to each other by the use of a pair of driving MOS transistors, and a load device (namely, pull-up device) is coupled to each output electrode.
Herein, the SRAM is generally classified into a CMOS (Complementary Metal Oxide Semiconductor) type and a high resistance load type. In this case, the MOS transistor is used as the load device of the flip-flop circuit in the CMOS type while a high resistance thin-film, such as polysilicon, is used as the load device in the high resistance load type.
With such a structure, MOS transistors for selecting addresses are connected to a pair of output electrodes, respectively. Thereby, one memory cell is structured.
In the CMOS type SRAM, one memory cell is structured by six MOS transistors. In consequence, one memory cell has a large occupied area in a semiconductor substrate.
In contrast, one memory cell is structured by four MOS transistors in the high resistance type SRAM, and the high resistance thin-film is formed at an upper portion of the MOS transistor. Thereby, the cell area can be reduced in the high resistance type SRAM.
In the meanwhile, when the cell area is reduced in the high resistance type SRAM, the memory cell having the high resistance load device consisting of the polysilicon must be formed by a laminate structure in a limited space. Consequently, the memory structure inevitably becomes complicated, and manufacturing step is also increased.
To solve such a problem, disclosure has been made about a specific SRAM in Japanese Unexamined Patent Publication (JP-A) No. Hei. 7-302847. In this SRAM, a memory cell is composed of a pair of driving MOS transistors and a pair of MOS transistors for selecting addresses.
In this event, each of the driving MOS transistors is structured by an N-type MOS transistor while each of the MOS transistors for selecting the addresses is structured by a P-type MOS transistors. With this structure, no load device is connected to an output node of each driving MOS transistor.
In this memory cell, the load devices, which are generally connected to the output nodes of the driving MOS transistors, are unnecessary. Thereby, the memory cell structure does not become complex. Further, the manufacturing step can be also reduced.
However, when the above-mentioned conventional SRAM is operated, an intimidate potential is inevitably necessary. In consequence, three kinds of potentials including a power supply potential (Vcc) and a ground potential (Vss) are required.
Specifically, the load device is unnecessary in the conventional SRAM, as mentioned before. Thereby, it is necessary to operate the MOS transistor for selecting the address as the load device in a stand-by operation.
To this end, electric elimination is compensated by flowing sub-threshold current into the MOS transistor for selecting the address. In order to flow the sub-threshold current, the intermediate potential is given to the MOS transistor for selecting the address.
Thus, a third potential (namely, the intermediate potential) must be set or prepared in addition to the two kinds of first and second potentials (namely, the power supply potential and the ground potential) which are originally necessary in the conventional SRAM.
This means that new other power supply circuit must be prepared. In consequence, a peripheral circuit of the SRAM becomes complex. Further, a circuit for generating the intermediate potential generally increases consumption current (namely, stand-by current) during the stand-by operation.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a semiconductor memory device which is capable of retaining a data signal of a memory cell without complicating a power supply structure and increasing stand-by current on the condition that a load device is unnecessary, and a method of manufacturing the same.
According to this invention, a semiconductor memory device has a first and second bit lines and a word line.
Further, the device includes a first MIS transistor for driving. In this event, the first MIS transistor has a first input electrode and a first output electrode and has a first conductive type and a first threshold voltage.
Moreover, the device includes a second MIS transistor for driving. In this event, the second MIS transistor has a second input electrode and a second output electrode and has the first conductive type and the first threshold voltage.
Herein, the first input electrode is connected to the second output electrode while the second input electrode is connected to the first output electrode.
Further, the device includes a third MIS transistor for selecting an address. In this event, the third MIS transistor is connected between the first bit line and the first output electrode and has a third input electrode and has a second conductive type and a second threshold voltage.
Herein, the third input electrode is connected to the word line and the second conductive type is opposite to the first conductive type.
In addition, the device includes a fourth MIS transistor for selecting an address. In this event, the fourth MIS transistor is connected between the second bit line and the second output electrode and has a fourth input electrode and has the second conductive type and the second threshold voltage. Herein, the fourth input electrode is connected to the word line.
With this structure, the first threshold voltage exceeds the second threshold voltage.
Each of the first and second MIS transistors includes a channel region. Further, a threshold voltage setting layer is placed in the channel region. In this condition, the first threshold voltage is set larger than the second threshold voltage via the threshold voltage setting layer. Herein, the threshold voltage setting layer includes impurity of the second conductive type.
Moreover, each of the first and second MIS transistors has first leak current while each of the second and third MIS transistor has second leak current. Under this circumstance, the second leak current exceeds the first leak current.
In consequence, sub-threshold current flows through each of said first and second MIS transistors when a power supply potential is given thereto during a stand-by operation.
For instance, the first conductive type is an N-type while the second conductive type is a P-type.
More specifically, the threshold voltage Vthn of each driving MOS transistor consisting of the N-type MOS transistor is set larger than a threshold voltage Vthp of each MOS transistor for selecting the address consisting of the P-type MOS transistor in the memory cell of the SRAM having no the load device.
In consequence, the data signal of the memory cell can be retained by using the two kinds of potentials (the normal power supply potential and the ground potential) without the third potential.
Namely, the leak current ILp of each MOS transistor for selecting the address becomes larger than the leak current ILn of each driving MOS transistor by satisfying the above-mentioned relationship (|Vthn|>|Vthp|). Namely, the relationship of (ILp>ILn) can be satisfied.
Thereby, when the power supply potential is given to
McGinn & Gibb PLLC
NEC Corporation
Trinh Michael
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