Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1997-12-18

2001-06-26

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S624000, C427S387000

Reexamination Certificate

active

06251805

ABSTRACT:

This application is based on Japanese Patent Application No. 8-355,582, filed on Dec. 24, 1996, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a). Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly relates to a method for forming a silicon oxide film that is suitable for use as an interlayer insulating film, passivation film, protective film, or other insulation film in a semiconductor device using a hydrogen silsesquioxane resin film.
b). Description of the Related Art
The use of a hydrogen silsesquioxane resin film to form an interlayer insulating film in a multilevel wiring structure was known in the past (see, for example, Japanese Laid-Open Patent Application JP-A 6-181204).
With an interlayer insulating film formation method such as this, the first step is to form a hydrogen silsesquioxane resin film on the surface of a semiconductor device by spin-coating or another method. The resin film is subjected to a heat treatment in an N
2
or other inert gas atmosphere to produce a silicon oxide film in a preceramic phase, and this silicon oxide film is then subjected to another heat treatment in an O
2
gas or other oxidizing atmosphere to convert the preceramic silicon oxide film into a ceramic-phase silicon oxide film. The silicon oxide in preceramic phase referred to here is a precursor of ceramic-phase silicon oxide, in which crosslinking is not as advanced as in ceramic-phase silicon oxide, but which is insoluble in organic solvents.
This method allows a silicon oxide film to be obtained with a thickness of at least 1 &mgr;m and without any cracks. This silicon oxide film is useful as an interlayer insulating film.
Research conducted by the inventors has revealed that the prior art discussed above leads to a lower yield in wiring formation because microscopic protrusions about 0.1 &mgr;m in diameter are produced on the surface of the ceramic-phase silicon oxide film.
FIGS. 11 through 15
illustrate a multilevel wiring formation method in which this prior art is applied.
In the step in
FIG. 11
, a wiring layer
14
is formed on a silicon oxide or other such insulation film
12
that covers the surface of a semiconductor substrate
10
, after which an insulation film
16
composed of silicon oxide is formed by plasma enhanced CVD (Chemical Vapor Deposition) so as to cover the insulation film
12
and wiring layer
14
. Hydrogen silsesquioxane resin is dissolved in methyl isobutyl ketone (MIBK), and the resulting solution is applied to the top surface of the substrate by spin-coating, which forms a hydrogen silsesquioxane resin film
18
A on the insulation film
16
such that the former has a flat surface.
In the step in
FIG. 12
, the hydrogen silsesquloxane resin film
18
A is subjected to a heat treatment in an inert gas atmosphere, which converts the hydrogen silsesquioxane resin film
18
A into a pre-ceramic-phase silicon oxide film
18
. The silicon oxide film
18
is then subjected to another heat treatment in a mixed atmosphere of O
2
gas an an inert gas, which converts the silicon oxide film
18
into a ceramic-phase silicon oxide film. The heat treatments performed here to produce a ceramic were conducted using a vertical heat treatment furnace as shown in FIG.
18
. These heat treatments will be described in detail below. It was found that as a result of these heat treatments, microscopic protrusions
18
a
with a diameter of about 0.1 &mgr;m were produced on the surface of the ceramic-phase silicon oxide film
18
.
In the step in
FIG. 13
, a conformal insulation film
20
composed of silicon oxide is formed by plasma enhanced CVD so as to cover the ceramic-phase silicon oxide film
18
. At this point, convex components
20
a
that faithfully reflect the microscopic protrusions
18
a
of the silicon oxide film
18
are formed on the insulation film
20
.
One problem related to the microscopic protrusions
18
a
and convex components
20
a
formed in this manner is that the shape of the connecting holes deteriorates as shown in
FIGS. 14 and 15
.
In the step in
FIG. 14
, a resist layer
22
having holes corresponding to the desired connecting holes is formed over the insulation film
20
, after which shallow connecting holes
24
a
are formed by selective wet etching (isotropic etching) in which the resist layer
22
serves as a mask. The connecting holes
24
a
serve to enhance the step coverage of the wiring by moderating the steps at the opening edges of deep connecting holes
24
b
shown in FIG.
15
.
If a 10:1 mixture of an NH
4
F aqueous solution and HF, for example, is used as the etching solution in the wet etching treatment shown in
FIG. 14
, then the etching solution will penetrate the microscopic protrusions
18
a
and nearby locations Q (locations that are shown by cross hatching) via the convex components
20
a
since the film is less dense at the convex components
20
a
and the wet etching is faster there.
Next, in the step in
FIG. 15
, connecting holes
24
b
that extend from the connecting holes
24
a
to the wiring layer
14
are formed by selective dry etching (anisotropic etching) in which the resist layer
22
serves as a mask. This etches away the microscopic protrusions
18
a
and the nearby dissolved locations Q, so concave components R are produced on the side walls of the connecting holes
24
b.
After the removal of the resist layer
22
, a wiring material is applied to the upper surface of the substrate to create a pattern, which forms a wiring layer (not shown) that extends to the wiring layer
14
via the connecting holes
24
and
24
b
. The wiring layer formed here has poor coverage at the places corresponding to the concave components R of the connecting holes
24
b
, so reliability suffers.
Another problem related to the microscopic protrusions and convex components is that short circuiting occurs between the wiring layers near convex components
20
b
corresponding to microscopic protrusions
18
b
, as shown in
FIGS. 16 and 17
. The microscopic protrusions
18
b
and convex components
20
b
are formed in the same manner as the above-mentioned microscopic protrusions
18
a
and convex components
20
a
, respectively.
After the step in
FIG. 13
, when the wiring material is applied to the upper surface of the substrate, and this application layer is patterned by selective etching to form a wiring layer, if the adjacent wiring layers
26
A and
26
B are formed in a shape that surrounds the convex components
20
b
as shown in
FIGS. 16 and 17
, part of the wiring material at the periphery of the convex components
20
b
will remain as etching residue
28
. The etching residue
28
puts the wiring layers
26
A and
26
B in a short-circuited state.
FIG. 18
illustrates the vertical heat treatment furnace used in the ceramic conversion step in
FIG. 12. A
plurality of heaters, such as
3
A to
3
C, are wound around the outside of a process pipe
1
composed of quartz or the like via a soaking pipe
2
which uniformalizes the incoming heat.
A lid member
4
, which is shown at the bottom in the figure, has a cylindrical member
5
, and supports a wafer holder
6
. A plurality of wafer support rods B
1
, B
2
, and so on are provided on the wafer holder
6
in an assembled state such that they are perpendicular to a plurality of linking members K
1
to K
4
. The plurality of wafer support rods are structured such that they are able to support 50 wafers WF in 50 groups of wafer support grooves made on the inner sides.
After the desired number of wafers WF have been loaded into the wafer holder
6
, the wafer holder
6
is inserted into the process pipe
1
in a state in which it is supported by the lid member
4
. The opening at the lower end of the process pipe
1
is closed by the lid member
4
and the cylindrical member
5
as shown in FIG.
18
.
A gas introduction pipe
1
a
is provided to the upper portion of the process pipe
1
, and the feed gas G
1
introduced into the process pipe
1
via the gas intr

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