Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-07-29
2001-09-18
An, Meng-Al T. (Department: 2154)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S045000, C714S047300, C714S724000, C714S742000, C714S703000
Reexamination Certificate
active
06292907
ABSTRACT:
The present invention generally relates to apparatus for monitoring the state machines of digital systems, and more particularly to an apparatus adapted to interface between the state machines and the output pins of a digital system for selecting a particular bit group from a plurality of state machine bit groups and transmitting the output of the selected bit group to the system output pins.
It is common in digital system environments to monitor the output bits of the state machines for purposes of “debugging” the system. Debugging is a way of determining whether a system has a “bug,” i.e., whether the system has been designed correctly, as opposed to checking the system for physical defects. One method of debugging a digital system is to examine the outputs and the inputs of the system, for example, keyboard presses, RAM accesses, etc. While this method may be effective in finding bugs which are readily detectable from the outside the system, it is inadequate in locating bugs which originate from within the system and cannot be detected from observing the inputs and the outputs of the system. One solution to this problem is to monitor the system state machines, which are abstract models of the circuitry indicating the states of the system. The state machines have a finite number of states, and therefore, they can be monitored to “view” the internal operation of the system. In this manner, the states of the state machines can be known at any particular time and the source of the bugs can be located.
A problem associated with monitoring the state machines is that the output bit lines of the state machines have to be connected to the output pins of the system. However, digital circuitry or systems are typically implemented on integrated chips, and as a result, there is a physical limitation as to the number of system output pins which may be connected to the state machine output bit lines. Typical digital systems have numerous groups of state machine bit lines, with each group having many bit lines. It would be impracticable in view of the physical constraints of the system to provide an output pin for each of the bit lines. One known solution to this problem is to have a microprocessor within the system select and connect only the bit lines of the state machine to be monitored to the output pins of the system. This solution, however, would not be effective if the microprocessor itself has a bug, or if the microprocessor is not operational.
Accordingly, it is a primary objective of the present invention to provide an improved apparatus for monitoring the state machines of a digital system.
Another object of the present invention to provide an improved apparatus for interfacing between the state machines and the output pins of the digital system.
Still another object of the present invention is to provide such an improved apparatus which allows the state machine bits to be output from the system without adding dedicated state machine output pins.
Yet another object of the present invention is to provide such an improved apparatus which selects a particular state machine bit group from a plurality of bit groups without employing a microprocessor.
A further object of the present invention is to provide such an improved apparatus having a minimal number of data input pins used in selecting the particular bit group.
REFERENCES:
patent: 4546472 (1985-10-01), Volk et al.
patent: 5202624 (1993-04-01), Gheewala et al.
patent: 5528364 (1996-06-01), Roohparvar
patent: 5604432 (1997-02-01), Moore et al.
patent: 5630048 (1997-05-01), Joie et al.
patent: 5646545 (1997-07-01), Trimberger et al.
An Meng-Al T.
El-Hady Nabil
Hewlett--Packard Company
LandOfFree
State machine bit group selection apparatus for debugging a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with State machine bit group selection apparatus for debugging a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and State machine bit group selection apparatus for debugging a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2545492