Semiconductor memory device having reduced component count...

Details Semiconductor memory device having reduced component count... Semiconductor memory device having reduced component count...

1999-03-15

2001-01-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

06175527

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a redundant memory circuit having less number of devices configuring the whole device and lower wiring density in the memory region.
2. Description of the Prior Art
A semiconductor memory device is a highly integrated device provided with a great number of memory cell array blocks, that is difficult to function normally if there is even only one defective memory cell within memory cell array blocks. Therefore, in semiconductor memory devices, optional defective lines or defective rows within the memory cell array blocks are replaced with redundant lines or redundant rows to make it function normally.
Recently, semiconductor memory devices are proposed that are made to function normally by replacing optional defective lines or defective rows in many memory cell array blocks with redundant lines or redundant rows provided independently from the memory cell array blocks, with the objective to raise the production yield of semiconductor memory devices by increasing the flexibility of replacement and raising the relief efficiency for defective memory cells.
A typical example of a conventional semiconductor memory device having redundant memory circuits for replacing by lines the memory cell lines of cell array blocks with is shown in FIG.
9
.
FIG. 9
is a block diagram of the circuit of a conventional semiconductor memory device.
As shown in
FIG. 9
, this semiconductor memory device
100
is provided with plurality (only four are shown in
FIG. 9
for simplicity) of cell array blocks
10
-
0
to
10
-
3
in which memory cells are located as basic memory circuits in plurality of lines and plurality of rows, a block selector
2
with which to select one from the cell array blocks
10
-
0
to
10
-
3
, a line predecoder
1
with which to designate a cell line to be selected from among the lines of the selected cell array blocks
10
, and line decoders
40
-
0
to
40
-
3
with which to select and drive a cell line according to orders from the line predecoder
1
.
The block selector
2
outputs block selection signals (BSL
0
to BSL
3
) for selecting one of the cell array blocks
10
-
0
to
10
-
3
based on the two higher bits of the line address signal (XA) which is input to the semiconductor memory device
100
.
The line predecoder
1
outputs predecoding signals (XDCS) for designating cell lines to be selected from the selected cell array blocks
10
by predecoding bit signals other than the higher two bits of the line address signals (XA).
Line decoders
40
-
0
to
40
-
3
are provided respectively corresponding to cell array blocks
10
-
0
to
10
-
3
, and when the corresponding line decoder activation signals (XDCE
0
to XDCE
3
) which are output from the array control circuit
3
described below are on the active level, select and drive cell lines designated by predecoding signals (XDCS) which are output from the line prdecoder
1
from the corresponding cell array block
10
.
Also, as shown in
FIG. 9
, the semiconductor memory device
100
, as a redundant memory circuit, is provided with plurality of redundant cell arrays
11
-
0
to
11
-
3
each comprised of one line amount of the redundant memory cell, plurality of replacement address program circuits
50
-
0
to
50
-
3
provided corresponding to the redundant cell arrays
11
-
0
to
11
-
3
, a replacement judging circuit
52
, a redundant line encoder
7
, plurality of array control circuits
3
-
0
to
3
-
3
provided corresponding to the cell array blocks
10
, and redundant line drivers
34
-
0
to
34
-
3
.
When there are defective lines in the cell array blocks
10
-
0
to
10
-
3
, the replacement address program circuits
50
-
0
to
50
-
3
will memorize line addresses corresponding to the defective lines, and output active level redundant line selection signals (XRD
0
to XRD
3
) when the line address signal XA designates line addresses of the defective lines.
The replacement judging circuit
52
outputs active level replacement judging signal (XRDN) when there are active level signals in the redundant line selection signals (XRD
0
to XRD
3
).
The redundant line encoder
7
is provided at a position close to the replacement address program circuits
50
-
0
to
50
-
3
, and encodes redundant line selection signals XRD
0
to XRD
3
that are output from the replacement address program circuits
50
-
0
to
50
-
3
and outputs them as redundant line selection encode signals (RXDS)
The array control circuits
3
-
0
to
3
-
3
are provided respectively corresponding to line decoders
40
-
0
to
40
-
3
and redundant line decoders
34
-
0
to
34
-
3
, and output active level line decoder activation signals (XDCE
0
to XDCE
3
) and sense activation signals (SAE
0
to SAE
3
) when the corresponding block selection signals (BSL
0
to BSL
3
) are on the active level and the replacement judging signal (XRDN) is on the inactive level, namely when the situation is normal.
On the contrary when the replacement judging signal (XRDN) is on the active level, namely in redundancy, they switch the line decoder activation signals (XDCE
0
to XDCE
3
) into inactive level as well as decode the redundant line selection encode signal RXDS, and then according to the results of decoding when the corresponding redundant line selection signals (XRD
0
to XRD
3
) are on the active level, output active level redundant line selection signals (RXDE
0
to RXDE
3
) and the sense activation signals (SAE
0
to SAE
3
).
The redundant line drivers
34
-
0
to
34
-
3
are provided each corresponding to redundant cell arrays
11
-
0
to
11
-
3
, and when the redundant line selection signals (RXDE
0
to RXDE
3
) are on the active level, select and drive the corresponding redundant cell array
11
.
Further, as shown in
FIG. 9
, the semiconductor memory device
100
has a row decoder
5
which selects one row of each of the cell array blocks
10
-
0
to
10
-
3
and the redundant cell arrays
11
-
0
to
11
-
3
, as a common circuit of a basic memory circuit and a redundant memory circuit, and sense amplifier circuits
6
-
0
to
6
-
3
having a transfer gate.
The line decoder
5
selects one row of each of the cell array blocks
10
-
0
to
10
-
3
and the redundant cell arrays
11
-
0
to
11
-
3
.
The sense amplifier circuits
6
-
0
to
6
-
3
having a transfer gate sense amplify the memory data of the memory cells where the selected lines and rows of corresponding cell array blocks
10
-
0
to
10
-
3
and redundant cell arrays
11
-
0
to
11
-
3
cross each other, and the memory data of redundant memory cells
11
-
0
to
11
-
3
.
Particular examples of circuits of an array control circuit
3
for four cell array blocks
10
-
0
to
10
-
3
, a line decoder
40
, and a redundant line decoder
34
are shown in
FIGS. 10
,
11
, and
12
respectively.
FIG. 13
is a circuit diagram of a memory region, and the memory region shown in
FIG. 13
is configured as having an array division number of
16
(selected by X
9
to X
12
), 64 main word lines (MWL)/array (selected by X
3
to X
8
), and 8 subword lines (SWL, redundant cell lines)/MWL (selected by X
0
to X
2
).
The array control circuit
30
is configured with two array activation signal generating circuits each corresponding to two upper and lower cell array blocks
10
, and two redundancy decode circuits.
As shown in
FIG. 10
, the array activation signal generation circuit is provided with a NAND gate (
11
) having input from two predecoding addresses for selecting main word lines (X
j+2N
X
j+3N
and X
jT
X
j+1N
, shown in
FIG. 13
as X
9N
X
10N
and X
11T
X
12N
respectively), and a NOR gate (
13
) which receives the output of the NAND gate (
11
) and the output of an inverter (
12
) receiving input of redundancy judgement signals (XREDUNB) which is outputted from a replacement judging circuit
52
, and outputs through the inverter
14
the BSELBm which is outputted from the NOR gate (
13
)

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