Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-27
2001-03-06
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000
Reexamination Certificate
active
06198137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device that is constituted by a plurality of memory cell transistors so as to form a memory cell array, such as a lateral-type ROM of a NOR gate type.
BACKGROUND OF THE INVENTION
In general, a ROM (Read Only Memory), utilized for writing various pieces of program information, has a MOS (Metal Oxide Semiconductor) transistor construction having a gate, a source and a drain combined in a matrix format, that is, a construction which has laminated metal, oxide (insulator) and semiconductors, and which cuts off or connects the source and the drain of the memory-use transistor, or sets two types of threshold values, in accordance with written information, so that it detects a current flowing between the drain and the source in a manner so as to correspond to “1” and “0” in stored information.
For example, as shown in FIGS.
7
(
a
) and
7
(
b
), such a conventional mask ROM of an NOR type with high integrity includes a P-type semiconductor (Si) substrate
51
, N-type semiconductor areas
57
, and gate electrodes
59
. Here, the N-type semiconductor areas
57
, formed into a plurality of stripes in one direction, are formed on an upper portion of the P-type semiconductor substrate
51
, and the gate electrodes
59
, formed into a plurality of stripes that extend perpendicular to these N-type semiconductor areas
57
through a gate oxidation film
58
, are also installed on the upper portion of the P-type semiconductor substrate
51
. Memory cells are placed at intersections between the N-type semiconductor areas
57
and the gate electrodes
59
.
Source areas and drain areas, made of the adjacent N-type semiconductor areas
57
, are located below the respective gate electrodes
59
, and operation channels
54
are formed between the source areas and the drain areas. In the case when the threshold voltage of each operation channel
54
is preliminarily set to a predetermined value for each portion, upon application of a voltage not less than the predetermined value to the gate electrodes
59
through word lines A
1
, A
2
. . . , the operation channels
54
are allowed to conduct, and electrons are allowed to shift from the source side toward the drain side (in this case, bit lines f
1
, f
2
. . . , have been preliminarily set so as to satisfy drain voltage>source voltage); thus, a drain current is allowed to flow. Consequently, the writing process for information “1” is carried out.
In other words, when a positive voltage is applied to the gate electrodes
59
, in the operation channel
54
, a positive hole of the P-type semiconductor substrate
51
is pushed inward, and in contrast, a negative charge that is an electron is induced. When the positive voltage of the gate electrodes
59
increases, the number of electrons in the operation channel
54
increases, with the result that an N-type transmitting layer is formed, and this allows the source area and the drain area that have the same N-type to conduct, thereby allowing a current to flow. Here, these transistors that form the N-type transmitting layer as the operation channel
54
are referred to as N-channel transistors. In contrast, those transistors that form the P-type transmitting layer as the operation channel
54
are referred to as P-channel transistors.
Here, in the case when boron (B) ions, which form an impurity to Si, are injected into the operation channel
54
, since B is trivalent while Si is tetravalent, in this boron (B) ion injected area
55
, there is a lack of one electron in order to form a covalent bond with an Si atom. Here, an attempt is made to compensate for the lack of one electron by gaining one electron from an adjacent Si atom so as to complete the covalent bond. As a result, a positive hole is formed at the original Si position.
When the concentration of boron (B) ions in the operation channel
54
is made high, the number of positive holes increases, with the result that even upon application of a predetermined positive voltage to the gate electrode
59
as described above, there is no increase in the number of electrons. This makes it possible to write information “0”.
In other words, in the mask ROM, data is fixed at the time of manufacturing a device. Therefore, as described above, when an attempt is made to write “0” upon application of a predetermined voltage, boron (B) ions are preliminarily injected into the operation channel
54
at a high concentration at the time of the manufacturing process thereof.
However, in the above-mentioned semiconductor device, as illustrated in FIG.
7
(
a
), the mask ROM of the NOR type needs 2F in the lateral direction pitch X per bit, and also needs 2F in the longitudinal direction pitch Y per bit, in the case of design rule F. For this reason, the area of the mask ROM of the NOR type occupies 4F
2
per bit, raising problems in achieving a small-size, highly integrated device.
Here, F in the above-mentioned design rule F refers to a dimension, for example, given as F=0.25 &mgr;m.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a semiconductor device which can achieve a small-size, highly integrated device by minimizing a separation area between respective elements in a transistor.
In order to achieve this objective, the semiconductor device of the present invention is provided with:
a first conduction type semiconductor substrate having a plurality of first conduction type semiconductor areas and a plurality of second conduction type semiconductor areas that are alternately formed adjacent to each other;
a first transistor having a source area and a drain area that are the second conduction type semiconductor areas and a channel section that is the first conduction type semiconductor area located between these;
a second transistor having a source area and a drain area that are the first conduction type semiconductor areas and a channel section that is the second conduction type semiconductor area located between these, the source or drain area being formed adjacent to the first transistor so as to serve as the channel section of the first transistor in a shared manner, one of the first and second transistors having a reversely biased coupling between the first and the second conduction type semiconductor areas while the other transistor is being operated.
With the above-mentioned arrangement, the first transistor and the second transistor are formed adjacent to each other on the first conduction type semiconductor substrate, and the channel section of the first transistor also serves as the source or drain area of the second transistor. However, in the case when transistors are simply placed adjacent to each other, current leakage might occur between the transistors.
For this reason, in conventional semiconductor devices, an element separation area is formed between the transistors so as to prevent current leakage. This needs to maintain an element separation area having a sufficient size, making it impossible to achieve a small-size, highly integrated semiconductor device.
In contrast, in the above-mentioned arrangement of the present invention, the first and second transistors are formed adjacent to each other, and in addition to this, in the transistor that is not being operated, the junction between the first and second conduction type semiconductor areas is reversely biased.
In other words, for example, while electrons are flowing from the source area to the drain area of the first transistor, a voltage lower than that of the drain area is applied to the area forming a junction with the drain area in the second transistor. Therefore, it is possible to avoid electrons from flowing out of the drain area, and consequently to positively prevent current leakage.
As described above, since the semiconductor device of the present invention has a construction for positively preventing current leakage between transistors without the need for installing an element separation area between transistors, it becomes possible to achieve further miniaturizatio
Meier Stephen D.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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