Processor-cache protocol using simple commands to implement...

Details Processor-cache protocol using simple commands to implement... Processor-cache protocol using simple commands to implement...

1997-05-06

2001-03-13

Etienne, Ario (Department: 2781)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S119000, C711S122000, C711S133000, C711S100000

Reexamination Certificate

active

06202125

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of computer systems; more particularly, the present invention relates to the field of cache memory arrangements in which a cache controller controls multiple cache memories at the same time and is compatible with multiple types of cache memories.
BACKGROUND
Cache controllers require very complicated logic and most computer systems contain two such controllers, one to control the first level (L
1
) cache within the processor and the other to control the second level (L
2
) cache in the system. The design of these two controllers is a compromise between performance and complexity of state that must be shared between them. A system of hierarchical caches would provide a higher overall performance if the cache controllers had access to information about accesses to all cache memories, along with information regarding the processor state and external bus accesses. This is clearly not possible when the cache controller for the L
2
cache memory is separate from the L
1
cache controller.
Also, in the prior art, processors communicate with cache controllers and L
2
cache memory by asserting and deasserting signals at specific pins. For example, a read is requested by asserting the read pin while sending the requested address to the L
2
cache memory. Thus, access to the cache memory begins when the signals are asserted or deasserted. In other words, prior art L
2
cache memories do not receive commands to be decoded and executed.
Furthermore, prior art L
2
caches are not designed to support more than one cache-processor architecture.
That is, prior art cache configurations are designed for specific processors or processor families. Different cache configurations typically are made having different balances between performance and cost. Because a cache configuration is designed for use with a specific processor family, the cost/performance balance of a computer system sought by the user may not be available. In fact, because of this dependence on a particular type of processor, the cache memory configuration cannot be upgraded with advances in technology independently of upgrading the processor. Thus, it is desirable to have a processor that is compatible with multiple types of cache organizations, including the option of operating without a cache memory (if so desired). Therefore, as the different organizations are upgraded, the microprocessor may not have to undergo any changes itself.
SUMMARY OF THE INVENTION
A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system includes a processor having a cache control circuit to control multiple cache memory circuits. The processor is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands from a set of commands that are decoded and executed by the second level cache memory.


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