Bit error measurement circuit

Details Bit error measurement circuit Bit error measurement circuit

1998-03-31

2001-07-24

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S819000

Reexamination Certificate

active

06266790

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bit error measurement circuit for evaluating a device such as an IC, a transmission device, a transmission line or the like. In particular, the present invention relates to a bit error measurement circuit which evaluates the above-described devices by using a test signal pattern set by a user arbitrarily.
2. Description of Related Art
In a bit error measurement, a test signal is transmitted by a transmitter and is received by a receiver through an object to be measured, e.g., a device such as an IC, a transmission device, a transmission line or the like. By carrying out a bit error measurement for the test signal received by a receiver, the measuring object is evaluated. In a pattern of the test signal, a pseudo-random pattern or a pattern set by a user arbitrarily is used frequently.
A transmitter transmits the test signal having the above-described pattern periodically and repeatedly. A receiver receives the test signal transmitted by a transmitter and memorizes one period of the test signal in a memory thereof by a pull-in operation, so that a reference signal is generated in a receiver. The following test signal transmitted by a transmitter is considered as a signal to be measured, and thereafter each bit of the signal to be measured is compared with that of the reference signal. As a result, bit errors are detected and are counted, so that a bit error rate is calculated.
In such a conventional bit error measurement circuit, for example, Japanese Patent Publication (Unexamined) No. Tokukai-Hei 8-149112 discloses a bit error measurement circuit. The conventional bit error measurement circuit will be explained in detail hereinbelow with reference to
FIGS. 6
to
9
.
FIG. 6
is a block diagram showing a composition of a conventional bit error measurement circuit
200
.
FIG. 7
is a block diagram showing a composition of a memory circuit
20
shown in FIG.
6
.
The compositions of the bit error measurement circuit
200
and of the memory circuit
20
will be explained.
In
FIG. 6
, the bit error measurement circuit
200
comprises the memory circuit
20
, an address counter
30
, a switching circuit
40
, an error detection circuit
50
, a gate circuit
51
, an error counter
60
and a clock counter
70
. Further, in
FIG. 6
, reference numeral
1
denotes an input terminal for a signal to be measured (a test signal)
1
a
,
2
denotes an input terminal for a clock signal
2
a
,
3
denotes an input terminal for a maximum address number
3
a
of the address counter
30
,
4
denotes an input terminal for an address counter control signal
4
a
,
5
denotes an input terminal for a pull-in signal
5
a
,
31
denotes an output terminal for an address carry-up signal
30
b
,
61
denotes an output terminal for a counted number
60
a
of errors and
71
denotes an output terminal for a counted number
70
a
of clock pulses.
In
FIG. 7
, the memory circuit
20
comprises two data input-output terminals
20
X and
20
Y, an address input terminal
20
A, a read-write control signal input terminal
20
RW and a switching signal input terminal
20
SW as external terminals. Further, the memory circuit
20
comprises a memory
201
and a switching circuit
202
therein. The memory
201
has a data input-output terminal
201
D, an address input terminal
201
A and a read-write control signal input terminal
201
RW. The switching circuit
202
has two switching terminals
202
X and
202
Y, a common terminal
202
Z and a switching signal input terminal
202
SW.
One switching terminal
202
X of the switching circuit
202
is connected with the data input-output terminal
2
OX of the memory circuit
20
. The other switching terminal
202
Y is connected with the data input-output terminal
20
Y of the memory circuit
20
. The common terminal
202
Z is connected with the data input-output terminal
201
D. The switching signal input terminal
202
SW is connected with the switching signal input terminal
20
SW of the memory circuit
20
. The address input terminal
201
A of the memory
201
is connected with the address input terminal
20
A of the memory circuit
20
. The read-write control signal input terminal
201
RW is connected with the read-write control signal input terminal
20
RW of the memory circuit
20
.
In
FIG. 6
, the signal
1
a
to be measured, which is inputted into the terminal
1
is inputted to a data input-output terminal
20
X. The address number
30
a
outputted from an address output terminal
30
OUT of the address counter
30
is inputted to the address input terminal
20
A. The read-write control signal
40
a
outputted from an output terminal
40
OUT of the switching circuit
40
is inputted to the read-write control signal input terminal
20
RW. The pull-in signal
5
a
inputted into the terminal
5
is inputted to the switching signal input terminal
20
SW.
When a logic value of the pull-in signal
5
a
inputted to the switching signal input terminal
20
SW is “0”, that is, when the pull-in operation is carried out, the switching circuit
202
of the inside of the memory circuit
20
shown in
FIG. 7
connects the common terminal
202
Z with the switching terminal
202
X. As a result, the signal
1
a
to be measured, which is inputted into the data input-output terminal
20
X is read and is written to the address which is indicated by the address number
30
a
inputted into the address input terminal
20
A, by the rise of the read-write control signal
40
a.
When a logic value of the pull-in signal
5
a
inputted to the switching signal input terminal
20
SW is “1”, that is, when the pull-in operation is not carried out, the switching circuit
202
of the inside of the memory circuit
20
shown in
FIG. 7
connects the common terminal
202
Z with the switching terminal
202
Y. As a result, the data of the address which is indicated by the address number
30
a
inputted into the address input terminal
20
A is read and is outputted from the data input-output terminal
20
Y to one input terminal
50
IB of the error detection circuit
50
as a reference signal
20
a.
The address counter
30
comprises a clock terminal
30
CLK, a maximum address number input terminal
30
AM, a reset terminal
30
RST, a carry-up signal output terminal
30
C and an output terminal
30
OUT. The clock signal
2
a
inputted into the terminal
2
is inputted to the clock terminal
30
CLK. The maximum address number
3
a
inputted into the terminal
3
is inputted to the maximum address number input terminal
30
AM. The address counter control signal
4
a
inputted into the terminal
4
is inputted to the reset terminal
30
RST.
When a logic value of the address counter control signal
4
a
inputted to the reset terminal
30
RST is “1”, that is, when the count operation is carried out, the address counter
30
carries out the count-up operation by the clock signal
2
a
inputted to the clock terminal
30
CLK and outputs the counted number from the output terminal
30
OUT to the address input terminal
20
A of the memory circuit
20
as an address number
30
a
. The counted number reaches the maximum address number
3
a
inputted into the maximum address number input terminal
30
AM, so that the counted number is reset. At the same time, a pulse signal is outputted from the carry-up signal output terminal
30
C to the terminal
31
as an address carry-up signal
30
b
and the count operation is carried out again.
When a logic value of the address counter control signal
4
a
inputted to the reset terminal
30
RST is “0”, that is, when the reset operation is carried out, the address counter
30
resets the counted number.
The switching circuit
40
comprises a data input terminal
40
X, a data input terminal
40
Y, a switching signal input terminal
40
SW and an output terminal
40
OUT. The clock signal
2
a
inputted into the terminal
2
is inputted to the data input terminal
40
X. A signal having a logic value “1” (High-level signal “H”) is inputted to the data input terminal
40
Y. The pull-in signal

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