Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-07-06
2001-01-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S425000
Reexamination Certificate
active
06174792
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a method of manufacturing a semiconductor device such as a power IC which includes lateral unit structures with high breakdown voltage. More specifically, the present invention relates to a method of manufacturing a semiconductor device which exhibits a breakdown voltage of 20 V or more.
In many conventional power IC's, a plurality of high-breakdown-voltage devices are integrated on one single chip. In the high-breakdown-voltage device, a drain side portion of a gate electrode is extended onto a LOCOS (local oxidation of silicon) film for device separation to relax the electric field localization below the drain-side edge of the gate electrode.
Recently, the structure of each high-breakdown-voltage device integrated on a chip has become so fine that the size of the constituent device affects greatly the down-sizing of the chip. When the LOCOS film for electric field relaxation is formed through an exclusive mask, an alignment mismatch of around 0.3 &mgr;m is caused between the LOCOS film and the gate electrode, and the LOCOS film is elongated by the alignment mismatch. When the device pitch (distance between the source and the drain) is 4 &mgr;m, for example, the chip size increases to 4.3 &mgr;m, i.e. around 8% (0.3 &mgr;m+4 &mgr;m).
FIG. 11
is a cross section of a main portion of a conventional lateral type DMOSFET with a high breakdown voltage. Here, the DMOSFET strands for “dual diffusion metal oxide semiconductor field effect transistor”.
Referring now to
FIG. 11
, a p-type base region
23
and an n-type offset region
21
are formed in the surface portion of a p-type silicon substrate
1
. An n-type source region
24
is formed in the surface portion of the p-type base region
23
. A polysilicon gate electrode
27
a
is formed above the p-type base region
23
and the p-type silicon substrate
1
between the n-type source region
24
and the n-type offset region
21
with a gate oxide film
2
interposed inbetween. The gate electrode
27
a
is extended onto a part of a LOCOS film
6
a
formed on the n-type offset region
21
. An n-type drain region
22
and a drain electrode
25
are formed on the right hand side of the n-type offset region
21
. Since LOCOS film
6
a
and gate electrode
27
a
are patterned through individual or different masks, the foregoing patterning mismatch (alignment mismatch) occurs. Due to the alignment mismatch, the overlap length D of the gate electrode
27
a
and LOCOS film
6
a
is elongated. As the overlap length D becomes longer, it is necessary to elongate the LOCOS film
6
a
for obtaining the design value of the breakdown voltage. As the device structure becomes finer as described above, the alignment mismatch can not be ignored. The device pitch (distance between the source and the drain) W becomes longer by the increment of the length of the LOCOS film
6
. The elongated device pitch enlarges the chip size.
As described above, the conventional technique causes the alignment mismatch as the device structure becomes finer. The alignment mismatch further causes the chip size increase.
In view of the foregoing, it is an object of the invention to provide a method of manufacturing a lateral type semiconductor device which facilitates shortening the device pitch without enlarging the chip size.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a method of manufacturing a semiconductor device, the method including the steps of: forming a gate oxide film on a semiconductor substrate; forming a gate electrode on the gate oxide film; forming a first nitride film on the gate electrode; etching the gate electrode and the first nitride film through a same mask; depositing a second nitride film for covering at least a side wall of the gate electrode; forming an opening in the second nitride film by anisotropic etching such that the second nitride film is left on the side wall of the gate electrode; and forming a thick oxide film in the bottom of the opening in the second nitride film by thermal oxidation.
The alignment mismatch between the gate electrode and the oxide film for the electric field relaxation is prevented by forming the gate electrode and the oxide film through the same mask. The first nitride film is deposited to prevent the gate electrode of polysilicon from being oxidized. And, the second nitride film left on the side wall of the gate electrode by anisotropic etching also prevents the gate electrode from being oxidized.
Advantageously, the thick oxide film is a LOCOS film for device separation.
By employing the LOCOS technique, a thick oxide film is obtained without adding any manufacturing step of thickening an oxide film. The semiconductor device according to the invention is of a lateral type.
Advantageously, the thick oxide film is formed for relaxing the electric field below the drain-side edge of the gate electrode.
REFERENCES:
patent: 5248350 (1993-09-01), Lee
patent: 61-244041 (1986-10-01), None
Fuji Electric & Co., Ltd.
Hoang Quoc
Kanesaka & Takeuchi
Nelms David
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