Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-07-29
2001-07-10
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S120000, C711S124000, C711S138000, C711S141000, C711S154000
Reexamination Certificate
active
06260118
ABSTRACT:
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A portion of the Disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent and Trademark Office, patent file or records, but otherwise reserves all rights in its copyright whatsoever.
RELATED PATENT FILING
This patent specification has been filed concurrently with and is cross referenced to assignee's related patent specification Ser. No. 08/856,272, pending.
TECHNICAL FIELD
This invention relates to snooping in multiple processor systems and more particularly to a snooping method and apparatus including a new system architecture which reduces the number of snoop cycles and effectively increases the available processor bus bandwidth.
BACKGROUND OF THE INVENTION
The limiting performance factor in most multiple processor systems is processor bus bandwidth. Since most multiple processor systems use processor caches, a significant percentage of the processor bus bandwidth is consumed in performing snoops of these caches during I/O operations. These snoop operations have a negative effect on overall system performance since they require a significant portion of the processor bus bandwidth.
Snoops are used during I/O operation to determine, by means of a controller, if the most recent copy in memory of a data item also resides in a processor cache. Systems which snoop, do so on a processor cache-line basis. To snoop a 4K byte page, in a system which has a 16 byte cache line, requires 256 snoop cycles. In systems that snoop, it is also required that the I/O and processor buses be synchronized for each of the snoop cycles. Consider the following, regarding the mechanism referred to as synchronization. In the example of a computer system with two busses, i.e., the processor bus and the I/O bus, if there is no transfer of information from one bus to the other bus then these busses can run independently of each other. However, if and when information is to be transferred from one bus to the other bus, then a mechanism must be created to allow this transfer and this can be done through synchronization. Synchronization can be implemented a number of ways and the following are two which are typical.
In a first example, the busses are run in lock step. This allows the transfer of information to occur at anytime. There are a number of disadvantages to the lock step design. The key being that as processor busses become faster, due to improvement in processor technology, this improvement may not be implemented or taken advantage of because of the requirement that the processor bus be synchronized (run at the same speed or at a multiple (2×, 3×, etc.) speed) to the I/O bus. A second typical example is of a latch interface. This is a storage device that is placed between the two busses. When data is to be transferred, one bus places the data into the latch and signals the other bus. The other bus then can access the storage device and signals the first bus that it has accessed the information. This need for synchronization can detrimentally lengthen the time required for the snoops, thereby increasing the load that snooping places on the multiple processor bus bandwidth.
One possible way of eliminating the snoop cycles on the processor bus would be to use processor caches which are store-thru. Unfortunately any bandwidth saved by eliminating the snoops, would be more than lost by the increase write-to-memory traffic. Therefore such a solution is not practicable and is not readily useful for multiple processor designs.
Store-thru, also called write-through strategy, provides for all memory writes from the microprocessor to be passed along immediately by a cache controller to also update the main system memory. The result is that the main system memory always contains valid data. Any location in the cache can be overwritten, i.e., updated, immediately without data loss. Further discussion of other related cache operations, upon which the specification relies, can be found in a booklet entitled “Cache Tutoral” available from Intel Corporation, Literature Sales, Mt. Prospect, Ill. The booklet is dated 1991 and the order number is 296543-002.
It would be advantageous to provide for snooping in a more efficient manner particularly for multiple processor systems without hindering access to the bus and unduly limiting bus bandwidth.
SUMMARY OF THE INVENTION
This invention introduces a system architecture which supports the concept of block snoops. Block snoops make the cache snooping operations more efficient by reducing the amount of traffic on the multiple processor bus. This in turn improves performance as well as increases the number of processors which can be supported at a reasonable level of performance, with a given bus design.
Significant features of the disclosed invention include, a bus interface unit or BIU which attaches between the caches of the processors and the multiple processor bus, and which includes two block snoop control registers. There is contemplated a BIU for each processor/cache subsystem; two unique signals which interface between the BIUs and the system memory controller; enhanced function within the memory controller to support not only I/O devices which support the block snooping function, but also other I/O devices which do not support the new block snooping function, which can be characterized as more vintage type I/O devices; and the use of a snoop table within the system memory controller to indicate which address of the physical memory can be safely transferred to I/O without the need for snooping during I/O operations.
Since this innovation introduces a new architecture, there is a software impact to its implementation. However, the impact is minimal and can be contained to just a set of device drivers and any busmaster I/O adapters which are set to implement this new function. The contemplated architecture is also backward compatible and busmaster devices which do not use or anticipate this function can still be used within a system which incorporates the invention.
The BIU which exists for each of the processor complexes, which complexes are connected to the multiple processor bus, is prepared with the following functions. There exists an interface to the processor complex, a start snoop address register, a block size register, a control logic to manage and control the block snooping function, including the two unique signals and also an interface to the multiple processor bus.
The uniqueness of the BIU allows the multiple processor bus to be processor independent. Therefore the concepts of the architecture of this invention can be applied to both x86 (Intel Corporation series processors and their compatibles) as well as RISC (reduced instruction set computing) processors. The BIUs interface to the memory controller through the multiple processor bus and the two unique signals. These two new signals comprise a signal from the BIU to the memory controller to indicate that the block snoop for this processor complex is completed, and a signal from the memory controller to all the BIUs indicating that each BIU should reset its respective start snoop address, register and block size register.
In addition with the present innovation there is no need to synchronize the busses. The present invention provides that when a block of data is to be moved between memory and an I/O device, wherein the address and number of bytes to be transferred are known, the system broadcasts on the processor bus this information to the processors, including the address and number of bytes. At each processor is provided a BIU which will independently generate a sequence of addresses causing the cache within the processor to be snooped. Depending on the result of each snoop operation, the caches will do one of three things. Under conditions where there is no match, the cache does nothing. Oth
Genduso Thomas B.
Leung Wan L.
International Business Machines - Corporation
Schelkopf J Bruce
Thai Tuan V.
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