Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-07-17
2001-01-09
Dutton, Brian (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000
Reexamination Certificate
active
06171946
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming a multilayered wiring pattern by which a fine wiring pattern of a multilayered structure is formed with high density, direct plotting equipment in which the method of forming is employed and electronic parts such as a multilayered wiring substrate manufactured by the method.
BACKGROUND OF THE INVENTION
Recently, the development of the miniaturization and high-density mounting of electronic parts used for electronic equipment has been carried out to respond to requests for multifunction capability, miniaturization and reduction in weight of electronic equipment such as personal computers and picture acoustic equipment. Especially, the design rule of semiconductor apparatus such as LSI has been hyperfined, the wiring pitch of the printed wiring substrate used for mounting the electronic parts with high density has been reduced to a minimum and multilayered wiring is formed on the printed circuit board.
The density of multilayered device such as multilayered printed wiring substrates and MCM multilayered substrate or devices on which multilayered structure wiring is formed such as LSI has been increased, so the demand has grown for a wiring pattern having a fine structure. On the other hand, it is also required for the device to be manufactured at low cost. It is very difficult to solve both the above-mentioned problems at the same time. One of the solutions concerning the production technique is such that the device is manufactured on a large scale. For example, in manufacturing multilayered printed circuit boards, it is very effective to manufacture a large number of printed circuit boards at a time by using one piece of large scale substrate, in the so-called multi-production technique, to reduce the production cost for each piece of the printed circuit board. In order to achieve the above-mentioned effect, in the printed circuit board industry, a process is employed in which a large scale square substrate having a side of about 500 mm is used to manufacture a large number of printed circuit boards. In addition to that, in the semiconductor substrate industry, a process in which a large number of LSI are formed on an 8-inch silicon wafer is employed. Taking advantage of high level heat-resistance, the change in size due to shrinkage caused by firing of the ceramic multilayered substrate used for electronic controller such as automobile is large, therefore, in general, a square ceramic multilayered substrate having a length about 100 to 300 mm, which is smaller than that of printed circuit board, is used.
Hereinafter, a conventional method of forming multilayered pattern such as the above-mentioned printed circuit board will be explained. FIGS.
5
A-
5
F show a process for forming a multilayered printed circuit board by a conventional manufacturing method. This conventional method of manufacturing a printed circuit board comprises the following steps:
(a) coating photosensitive insulating layer
505
on a top surface of glass epoxy multilayered wiring board
504
comprising an inside wiring pattern
501
, a top surface wiring pattern
502
and a bottom surface wiring pattern
503
(as shown in FIG.
5
A);
(b) locating a first mask
506
on which a pattern is formed to form a via hole to fit the top surface wiring pattern
502
formed on the insulating layer
505
(as shown in FIG.
5
B);
(c) removing the insulating layer
505
at the position of a via hole to be punched by exposing over the first mask
506
by photolithography to form a via hole
507
(as shown in FIG.
5
C);
(d) activating the inside wall of the via hole
507
with Sn-Pd to give conductivity and plating Cu to form a conductive layer
508
on the whole surface of the inside wall of the via hole
7
(as shown in FIG.
5
D);
(e) locating a second mask having a pre-designed wiring pattern on the conductive layer
508
(as shown in FIG.
5
E); and
(f) exposing by the photolithography or etching to form a wiring pattern
510
to be achieved(as shown in FIG.
5
F).
A basic method of manufacturing a semiconductor device such as an LSI device is the same as that of the above-mentioned method of manufacturing a printed circuit board. The method of manufacturing a semiconductor device comprises the following steps:
(a) forming a bottom side wiring pattern of an aluminum deposited film or sputtered film on a top surface of silicon wafer on which an active element or a passive element is formed;
(b) covering the bottom side wiring pattern with a dielectric layer composed of silicon oxide and forming a via hole by photolithography;
(c) forming a conductive layer by sputtering or depositing; and
(d) forming a top side wiring pattern by photolithography in the same way. In the above-mentioned process of forming a wiring pattern of an LSI, the accurate positioning of the mask is required when photolithography is employed in the same way as that of the method of manufacturing a printed circuit board. Further, a passive element and an active element are manufactured by repeating photolithography a plurality of times.
As above-mentioned, the number of electronic parts per one piece of work substrate (one piece of unit substrate on which a large number of electronic parts are multi-produced at the same time, for example, an 8-inch silicon wafer for LSI) has to be increased in order to reduce the production cost of the electronic parts of the printed circuit board or LSI. However, in the above-mentioned conventional method of forming a wiring pattern, the size of the work substrate becomes bigger, and accuracy of positioning becomes lower. In addition to that, the coefficient of thermal expansion of the mask, the substrate material and the conductive layer used in the conventional method of forming are different, therefore a difference of size is caused and consequently the yield is lowered. For example, a printed circuit board comprising glass epoxy as substrate comprises inorganic glass fiber and organic epoxy resin in the substrate and a wiring pattern composed of metallic material is formed thereon. Accordingly, in general, the thermal expansions of the materials composing the printed circuit board are different and during the manufacturing process, the material is stressed by applying pressure and heat. Therefore it is very difficult for photolithography to improve the size accuracy which a plurality of material is layered and mask is aligned. Further, as the number of layers in the wiring patterns increases, the difficulty of improving the size accuracy increases accordingly.
FIG. 6
shows an example of a work board for multi-production employed in a general method of forming a wiring pattern. As shown in
FIG. 6
, twenty five pieces of printed circuit boards
602
on which a wiring pattern
604
and a via hole
605
are formed are formed by using work board
601
. Element
603
indicates a reference bore which is used to maintain the accuracy of the size in aligning the mask when photolithography is employed. As shown in
FIG. 7
, due to the change of size caused by thermal expansion, some parts of via hole
605
for connecting a wiring pattern
604
of the surface layer with a wiring pattern
701
of the under layer can not be accurately positioned. When some part of via hole
605
deviates as indicated by
605
a,
the electrical connection becomes unstable, and the reliability of the manufactured product is lowered. Further, when the position of the via hole deviates entirely, as indicated by
605
b,
the manufactured product becomes inferior, and production yield is lowered.
In general, when a square work board having 500 mm side is used, it is difficult to make a size error in positioning of 100 &mgr;m or smaller. As mentioned above, when the density of wiring pattern becomes higher, the difficulty of reducing size error in positioning increases.
This invention provides a method of forming multilayered wiring patterns in which respective wiring patterns can be formed with high accuracy without being affected by the change of size caused by diffe
Dutton Brian
Matsushita Electric - Industrial Co., Ltd.
Morrison & Foerster / LLP
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