Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-10-26
2001-05-08
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S295000, C327S141000, C327S155000, C327S161000
Reexamination Certificate
active
06229368
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices that generate internal clock signals.
BACKGROUND OF THE INVENTION
Integrated circuit devices, such as high speed semiconductor memory devices, typically input and output data in-synch with an externally applied clock signal. For example, in a high speed semiconductor memory device, data input and output operations may utilize an internal clock signal synchronized with the phase of the external clock signal. The internal clock signal is typically generated by an internal clock signal generating circuit using a delay locked loop (DLL) circuit.
The internal clock signal is transmitted to various internal circuits using a clock signal to control their operation, such as input and output circuits placed near input and output pads, via a clock line. The transmitted clock signals, referred to as a local clock signals in the vicinity of the internal circuits, drive an associated input and output circuit.
However, in a conventional high speed semiconductor memory device, clock lines typically take the form of a clock net which has a clock tree structure. The tree structure transmits the internal clock signal from an output port of the internal clock signal generating circuit to a plurality of internal circuits such as input/output circuits. A clock tree typically has different loads, i.e., different parasitic resistances and parasitic capacitances depending on its length. Therefore, the delay time generally varies according to the length of the clock tree. Accordingly, a phase difference may be generated between the transmitted local clock signals in the vicinity of the input/output circuits. The data input/output performance of integrated circuit devices, such as a high speed semiconductor memory devices, may be degraded as a result of the phase difference.
In another aspect of internal clock generation, a conventional internal clock signal generating circuit used in devices, such as high speed semiconductor memory devices, typically includes a conventional Delay Lock Loop (“DLL”) circuit. The DLL circuit generally includes a delay monitoring circuit which generates a delay time intended to be the same as a delay time produced by the internal circuits carrying the internal clock signal including, for example, a clock signal buffer, a clock signal line, and an input/output circuit. Such a conventional DLL circuit typically generates an internal clock signal using the phase difference between a feedback clock signal output by the delay monitoring circuit and an external clock signal. However, the delay monitoring circuit in such a conventional DLL circuit typically has a complicated design, has a large layout area, and consumes a large amount of power. Also, when temperature, supplied voltage, noise, and/or the manufacturing process are changed, the delay time generated by the delay monitoring circuit may become widely different from the delay time generated by the clock net and the input/output circuits. Therefore, the performance of the high speed semiconductor memory device can be degraded.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a circuit for generating a plurality of local clock signals which may have no phase difference between the local clock signals.
It is a further object of the present invention to provide a clock generating circuit which may perform consistently independently of the manufacturing process, temperature, supplied voltage, noise and other variables which may affect integrated circuit performance.
In order to provide for the foregoing objectives, an integrated circuit device is provided having a local clock signal generating circuit including a phase blender circuit which receives an internal clock signal from at least two displaced points on an internal clock signal line. The internal clock signal from the two points is blended to compensate for delay caused by the characteristics, such as the impedence, of the internal clock signal line to provide a local clock signal to an internal circuit in the vicinity of the local clock signal generating circuit. The local clock generating circuit further includes one or more additional phase blender circuits that receive signals from additional pairs of points and generate additional local clock signals for other internal circuits. In a preferred embodiment, each phase blender circuit receives one input signal from a forward line of the internal clock signal line and a second input from the backward (return) line of the internal clock signal line in the vicinity of each phase blender circuit with each phase blender circuit, in turn, being in the vicinity of the internal circuit receiving the output local clock signals of the respective phase blender circuits.
The internal clock generating aspects of the present invention are provided by a feedback clock generating circuit in the internal clock generating circuit which generates a dummy clock signal from a dummy phase blender circuit and delays the dummy clock signal by a delay circuit configured to introduce a delay corresponding to the delay of the internal circuits receiving the local clock signals. The phase of the internal clock signal and the local clock signals may thereby be matched, preferably regardless of variables, such as temperature, supplied voltage and other variables, which may affect the performance of conventional internal clock generating circuits.
In one embodiment of the present invention, an integrated circuit device is provided including a first phase blender circuit having a first input coupled to a first point on a clock signal line and a second input coupled to a second point on the clock signal line displaced from the first point. A local clock signal output is generated by the first phase blender circuit responsive to the first input and the second input. A second phase blender circuit is also included having a third input coupled to a third point on the clock signal line displaced from the first point and the second point and a fourth input connected to a fourth point on the clock signal line displaced from the first, second, and third point. A second local clock signal output is generated by the second phase blender circuit responsive to the third input and the fourth input. Preferably, the local clock output of the first phase blender circuit and the local clock output of the second phase blender circuit have substantially no phase difference.
In a particular embodiment of the present invention, the clock signal line includes a forward clock signal line connected from an internal clock generating circuit of the integrated circuit device and a backward clock signal line connected from the vicinity of an internal circuit of the integrated circuit device remote from the internal clock generating circuit to the vicinity of the internal clock generating circuit. The first point and the third point are connected to the forward clock signal line and the second point and the fourth point are connected to the backward clock signal line.
In a further embodiment of the present invention, each of the phase blenders includes a first inverter coupled to the first input and a second inverter coupled to the second input. A third inverter having inputs coupled to outputs of the first inverter and the second inverter provides the local clock signal output of the first phase blender.
In a further aspect of the present invention, the integrated circuit device includes an internal clock signal generating circuit that generates an internal clock signal on the clock signal line responsive to an external clock signal. The internal clock signal generating circuit includes a delay line circuit that delays the external clock signal to provide the internal clock signal and a delay monitoring circuit that generates a feedback clock signal responsive to a delay time of the clock signal line. The internal clock generating circuit further includes a phase detector circuit coupled to the feed
Myers Bigel & Sibley & Sajovec
Nguyen Hai L.
Samsung Electronics Co,. Ltd.
Wells Kenneth B.
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