Semiconductor memory capable of burst operation

Details Semiconductor memory capable of burst operation Semiconductor memory capable of burst operation

1998-12-17

2001-01-30

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S220000

Reexamination Certificate

active

06181612

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory capable of operating in burst mode and, more particularly, to a high-speed semiconductor memory used illustratively as a cache memory.
2. Description of the Related Art
There exist semiconductor memories capable of the so-called burst output. Such semiconductor memories include an address counter and a memory cell array. The address counter operates in response to a clock signal input. When read from memory cells in the memory cell array, the data is output in accordance with the result of the counting by the address counter.
FIG. 12
is a block diagram of a typical conventional SCRAM capable of operating in burst mode. Referring to
FIG. 12
, the SCRAM comprises a memory cell array
1
, a decoder
2
, a bit line pre charging circuit
3
, a sense amplifier and write driver
4
, registers
21
and
23
, a read/write control circuit
22
, and a burst counter unit
80
.
The memory cell array
1
includes a plurality of memory cells MHC, MHC, etc., a plurality of word lines
11
,
11
, etc., and a plurality of bit line pairs
12
,
12
, etc. The memory cells MC, MC, etc. Constitute a matrix made of rows and columns, each cell accommodating data.
Each memory cell MC comprises two access transistors
13
and
14
, two driver transistors
15
and
16
, and two load resistors
17
and
18
. The access transistors
13
and
14
and the driver transistors
15
and
16
are an n-channel MOS transistor each. The load resistors
17
and
18
are each composed of a resistance element, a p-channel MOS transistor or a thin film transistor.
The load resistor
17
and the driver transistor
15
are connected in series between a power supply node N
1
that receives a supply potential and a grounding node N
2
that receives a grounding potential. The load resistor
18
and the driver transistor
16
are also connected serially between the two nodes N
1
and N
2
. The driver transistors
15
and
16
have their gate and drain electrodes connected by intersection.
The access transistor
13
has its gate electrode connected to a word line
11
. The access transistor
13
is connected interposing between one of the two bit lines constituting a bit line pair
12
,
12
on the one hand, and the connection node (storage node) between the load resistor
17
and the driver transistor
15
on the other hand.
The access transistor
14
has its gate electrode connected to the word line
11
. The access transistor
14
is connected interposing between the other of the two bit lines constituting the bit line pair
12
,
12
on the one hand, and the connection node (storage node) between the load resistor
18
and the driver transistor
16
on the other hand.
The word lines
11
,
11
, etc. Are each furnished to select the memory cells arranged thereon. The bit line pairs
12
,
12
, etc. Are each provided to transfer write and read data to and from the memory cell MC selected by the applicable word line
11
.
An input pin
91
admits a clock signal CLK from the outside. An input pin
93
receives an advance signal ADV that is externally furnished. An input pin
94
receives an externally provided address strobe signal ADS. An input pin
100
admits an external address signal EXT.ADD from the outside. An input pin
101
gets a read/write control signal /WE furnished externally. The slash symbol (/) indicates that the signal having the symbol is an inverted signal. This applies throughout the description hereunder.
The burst counter unit
80
includes AND gates
81
and
82
, a register
83
and a burst counter
84
. The AND gate
81
receives the advance signal AD and clock signal CLK, and outputs a signal representing the result of the AND operation on the two signals. The AND gate
82
admits the address strobe signal ADS and clock signal CLK, and outputs a signal denoting the result of the AND operation on the two signals.
The register
83
receives both the output signal of the AND gate
82
and the external address signal EXT.ADD. In operation, the register
83
takes the external address signal EXT.ADD into the burst counter unit
80
in response to the output signal from the AND gate
82
. The n-bit address admitted into the register
83
is separated into a k-bit address and an (n-k)-bit address.
The burst counter
84
is a binary counter that receives the output signals of the AND gates
81
and
82
, and the k-bit address following the address separation. In operation, the burst counter
84
loads the k-bit address by responding to the output signal of the AND gate
82
, and increments the value of the k-bit address in reply to the output signal of the AND gate
81
.
The k-bit address representing the result of the counting by the burst counter
84
is then recombined with the separated (n-k)-bit address. The result is an n-bit internal address that is fed to the decoder
2
. Given the n-bit internal address signal INT.ADD, the decoder
2
selects one word line
11
.
The register
21
receives the clock signal CLK and the read/write control signal /WE. The read/write control signal /WE is admitted into the register
21
responding to a leading edge of the clock signal CLK. The read/write control signal /WE indicates a write state when brought Low, and denotes a read state when driven High. The read/write control circuit
22
outputs a control signal for controlling the bit line pre charging circuit
3
and the sense amplifier and write driver
4
in reply to the read/write control signal /WE admitted through the register
21
.
Given the control signal from the read/write control circuit
22
, the bit line precharging circuit
3
precharges a bit line pair
12
,
12
to a predetermined high level in preparation for a read operation. Upon receipt of the control signal from the read/write control circuit
22
, the sense amplifier and write driver
4
operates as follows:
In the write operation, the sense amplifier and write driver
4
transfers to the bit line pair
12
,
12
the input data DI admitted into the register
23
from the outside via a data input/output pin
9
.
The conventional SRAM of the above constitution typically works as follows: when the advance signal AD is brought High, the address on the burst counter
84
is incremented every time a leading edge of the clock signal CLK is encountered. As the internal address signal INT.ADD is incremented in this manner, the decoder
2
selects different word lines
11
successively.
Below is a description of how the SRAM of
FIG. 12
works in a read operation.
FIG. 13
is a timing chart showing typical waveforms of signals used by the SRAM of
FIG. 12
in the read operation.
Referring to
FIGS. 12 and 13
, the read/write control signal /WE is fixed to the high level for the read operation. When a leading edge of the clock signal CLK is encountered, the address strobe signal ADS is brought High. This allows the external address input signal EXT.ADD to be admitted into the register
83
.
Thereafter, every time the clock signal CLK is at a leading edge and the advance signal ADV is High, the address indicated by the internal address signal INT.ADD based on the address An given by the external address signal EXT.ADD is incremented by the burst counter
84
. The incremented address occurs as An, An+1, An+2, etc.
This causes a different word line
11
to be selected in each cycle of the clock signal CLK. As a result, the output data DO varies in the sequence of Qn, Qn+1, Qn+2, etc. This in turn allows data to be output in burst mode from memory cells MC, MC, etc. In the memory cell array
1
.
Below is a description of how the SRAM of
FIG. 12
works in a write operation.
FIG. 14
is a timing chart showing typical waveforms of signals used by the SRAM of
FIG. 12
in the write operation.
Referring to
FIGS. 12 and 14
, the read/write control signal /WE for the write operation is given as a pulse signal as opposed to the high-level signal used in the read operation. The input data DI (Dn, Dn+1, Dn+2, etc.) Is admit

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