Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-01-14
2001-01-30
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S230030, C365S185210
Reexamination Certificate
active
06181622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory.
2. Description of the Related Art
Generally, in the data read operation of a dynamic random access memory (DRAM) as a semiconductor memory, a predetermined data as stored is first transmitted from a memory cell to a sense amplifier through a column switch, thereby being amplified there. This amplified data is further transmitted to an output circuit and is then read out to the outside of the DRAM.
In a prior art DRAM, when transmitting the read data from the sense amplifier to the output circuit, the sense amplifier and the output circuit have been controlled by an address transition detection signal (referred to as “signal ATD” hereinafter) and a data read control signal (referred to as “signal WE” hereinafter).
In general, in case of the DRAM which includes a complementary data line provided between the sense amplifier and the output circuit, the sense amplifier is controlled by the signal ATD and signal WE, and the input of the read data to the output circuit is executed in response to the level transition of the complementary data line.
Recently, however, the ATD signal speed has been made higher in association with the access speed to the DRAM. Thus, in such a DRAM that its output circuit is controlled by the ATD signal in order to stabilize the input of the read data to the output circuit, it is needed to provide a delay circuit for delaying the ATD signal, in order to provide a predetermined margin for the input timing of the read data.
On one hand, in such a DRAM that the input of the read data to the output circuit is carried out in response to the level transition of the complementary data line, it is not necessary to provide any delay circuit for delaying the ATD signal. In this case, however, it is absolutely required to provide the complementary data line. Contrary to this, in case of a so-called single data line DRAM which is provided with no complementary data line for the purpose of reducing the chip area, such a delay circuit as mentioned above has to be provided inevitably.
Generally, in the DRAM, a plurality of sense amplifiers and output circuits are controlled in the same timing. Therefore, if the number of sense amplifiers and output circuits is increased to comply with the increase in the memory capacity, the noise generation caused when reading the data comes out as another problem to be concerned with.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of such problems as described above. Accordingly, the first object of the invention is to provide a semiconductor memory which can not only minimize the enlargement of the circuit scale but comply with the high speed access, and the second object of the invention is to provide a semiconductor memory which can prevent the noise generation which might be caused when reading the data.
In order to achieve the objects as described above, according to the invention, there is provided a semiconductor memory which includes n sense amplifiers (n: an integer of two and more) which amplify the data as stored and output the amplified data as the read data, and n output circuits (n: an integer of two and more) which output the output data based on the read data outputted from each of the sense amplifiers. Each of the sense amplifiers provided in this semiconductor memory includes a read data transition detection circuit which detects that there has been decided the level transition of each read data to be outputted to each of the output circuits, and outputs a read data transition detection signal. Each of the output circuits receives the read data outputted from each of the sense amplifiers in response to the read data transition detection signal outputted from the read data transition detection circuit which is provided in each of the corresponding sense amplifiers. According to the constitution of the semiconductor memory as described above, even if the semiconductor memory employs a single data line structure, there can be achieved the high speed input of the read data to each of the output circuits.
Each of the output circuits receives the read data outputted from each of the sense amplifiers based on all the read data transition detection signals which indicate that there have been decided all the level transitions of the read data outputted from each of the sense amplifiers. The semiconductor memory of the invention may be further provided with a first control circuit which detects that all the level transitions of the read data have been decided, and outputs all the read data transition detection signals. According to the semiconductor memory as constituted above, each output circuit can judge the level transitions of the read data outputted from n sense amplifiers at a time, based on all the read data transition detection signals. That is, it becomes possible not only to minimize the enlargement of the circuit scale but to input the read data to each of the output circuit at the high speed.
The first control circuit outputs a reset signal all the time until all the sense amplifiers output the read data transition detection signals, after any one of n sense amplifiers having decided the level transition of the read data at first, has outputted the read data transition detection signal. Each of the output circuits preferably sets its output node for putting out the output data in the high impedance state in response to the reset signal. According to the constitution as describe above, it becomes possible to reduce the power consumption in each output circuit and also to prevent the output noise from being generated.
The first output circuit of n output circuits sets its first output node for putting out the output data in the high impedance state in response to the reset signal, and receives the read data outputted from the corresponding sense amplifier in response to the all the read data transition detection signals; the second output circuit of n output circuits sets its second output node in the high impedance state based on that the first output node is set in the high impedance state, and receives the read data outputted from the corresponding sense amplifier based on that there has been decided the level transition of the output data outputted from the first output circuit; and the kth output circuit (k: an integer of three through n) of n output circuits sets its kth output node in the high impedance state based on that the k−1th output node of the k−1th output circuit is set in the high impedance state, and receives the read data outputted from the corresponding sense amplifier based on that there has been decided the level transition of the output data outputted from the k−1th output circuit. According to the constitution as described above, since each node in n output circuits is once set in the high impedance state, it becomes possible to reduce the power consumption in each output circuit and also to prevent the output noise from being generated. Moreover, since each output circuit comes to receive the read data outputted from each sense amplifier on the read data by read data basis, it becomes possible to further reduce the noise generation which might take place when receiving the read data and/or outputting the output data.
The n output circuits can be divided into m output circuit groups (m: an integer of two or more). The first control circuit is assigned to the first output circuit group while the ith control circuit (i: an integer of two through m) is assigned to the ith output circuit group. The first control circuit supplies all the read data transition detection signals and the reset signal to one or more than two of output circuits belonging to the first output circuit group. The ith control circuit sets the output nodes in one or more than two of output circuits in the high impedance state based on that the output node in at least one output circuit of one or more than two of output circuits belonging to the i−1th output circ
Fears Terrell W.
Jones Volentine, L.L.C.
OKI Electric Industry Co., Ltd.
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