Complementary MOS device

Details Complementary MOS device Complementary MOS device

1999-03-01

2001-03-06

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000

Reexamination Certificate

active

06198139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, and more specifically to a semiconductor device having active regions of different conductivity types on a semiconductor substrate and a method of manufacturing the device.
2. Description of the Background Art
Conventionally, as an example of a semiconductor device having active regions of different conductivity types on the same semiconductor substrate, a complementary MOS (metal oxide semiconductor) device (hereinbelow simply referred to as “CMOS”) is known which is configured by a p-channel MOS transistor and an n-channel MOS transistor.
A conventional CMOS is disclosed, for example, in Japanese Patent No. 2660056 (Japanese Patent Laying-Open No. 3-99464). There is a need for established miniaturization techniques that accompany the higher density and higher degree of integration achieved in a CMOS while maintaining its low power consumption characteristic is maintained.
Structurally, a parasitic bipolar transistor circuit is formed inside a CMOS. Since this bipolar transistor circuit has the same configuration as a thyristor, when the circuit is triggered by a surge or the like from outside, excessive current flows from a power supply terminal, and the so-called latchup phenomenon occurs, where the current continues to flow even after the surge or the like no longer exists. This latchup can destroy the device.
Since the latchup phenomenon more readily occurs as the element is miniaturized, a new structure is required which improves latchup resistance as a CMOS is further miniaturized. One example is a retrograde well structure using an epitaxial layer.
FIG. 18
shows a cross sectional view in which a CMOS inverter is formed upon an epitaxial wafer having a thin epitaxial layer formed on a silicon substrate. In addition,
FIG. 18
also shows an equivalent circuit diagram of a parasitic thyristor.
As shown in
FIG. 18
, a p
−
epitaxial layer
3
a
is formed on the main surface of a p
+
silicon substrate
1
a
. On the boundary portion between p
−
epitaxial layer
3
a
and silicon substrate
1
a
, a p-type impurity region
2
a
is formed. An n-well
4
and a p-well
5
are formed adjacent to each other in p
−
epitaxial layer
3
a
. Moreover, a field oxide film
6
is selectively formed on a surface of p
−
epitaxial layer
3
a.
A p MOS transistor is formed on n-well
4
, and an n MOS transistor is formed on p-well
5
. The p MOS transistor is provided with a source region
8
a
, a drain region
8
b
, and a gate electrode
7
a
. The n MOS transistor is provided with a source region
9
a
, a drain region
9
b
, and a gate electrode
7
b.
Side wall insulating films
12
are formed on the sidewalls of gate electrodes
7
a
,
7
b
. Moreover, an n-well contact region
10
is formed on n-well
4
, and a p-well contact region
11
is formed on p-well
5
.
N-well contact region
10
and source region
8
a
are connected to a power supply voltage Vcc, gate electrodes
7
a
,
7
b
are connected to an input terminal, and drain regions
8
b
,
9
b
are connected to an output terminal. Further, source region
9
a
and p-well contact region
11
are grounded (GND).
In the above-mentioned configuration, a parasitic vertical pnp bipolar transistor
16
a
with source region
8
a
serving as an emitter, n-well
4
as a base, and silicon substrate
1
a
as a collector, and a parasitic lateral npn bipolar transistor
17
a
with source region
9
a
serving as an emitter, p-well
5
as a base, and n-well
4
as a collector are formed. A parasitic thyristor is formed from parasitic vertical pnp bipolar transistor
16
a
and parasitic lateral npn bipolar transistor
17
a.
N-well
4
has a retrograde well structure with a bottom portion having a high impurity concentration. Thus, parasitic resistance RW becomes small, and the difference in potential between the base and the emitter of parasitic vertical pnp bipolar transistor
16
a
also becomes small. Consequently, parasitic vertical pnp bipolar transistor
16
a
does not turn on easily. In addition, the impurity concentration in the region corresponding to the base of parasitic vertical pnp bipolar transistor
16
a
is high, causing more recoupling in the base and leading to a lower current amplification factor of parasitic vertical pnp bipolar transistor
16
a.
Moreover, the use of p
+
silicon substrate
1
a
reduces parasitic resistance RS, and the difference in potential between the base and the emitter of parasitic lateral npn bipolar transistor
17
a
becomes small. Thus, parasitic lateral npn bipolar transistor
17
a
does not turn on easily. In addition, the impurity concentration in the region corresponding to the base of parasitic lateral npn bipolar transistor
17
a
becomes high, resulting in more recoupling in the base and leading to a smaller current amplification factor of parasitic lateral npn bipolar transistor
17
a.
Therefore, the loop gain of the parasitic thyristor formed by parasitic vertical pnp bipolar transistor
16
a
and parasitic lateral npn bipolar transistor
17
a
can be suppressed and latchup resistance may be improved.
In particular, the effect of reduced base resistance of parasitic lateral npn bipolar transistor
17
a
by the use of p
+
silicon substrate
1
a
largely contributes to the improvement in latchup resistance. Through the use of p
+
silicon substrate
1
a
, base resistance of parasitic lateral npn bipolar transistor
17
a
is reduced to one or two orders of magnitude smaller than that in the case of a typical wafer. As a result, the current required to forward bias the pn junction between the base and the emitter of parasitic lateral npn bipolar transistor
17
a
becomes extremely large. Since this current is provided by the collector current of parasitic vertical pnp bipolar transistor
16
a
, parasitic vertical pnp bipolar transistor needs to conduct a large current, resulting in high level injection region operation. Thus, the current amplification factor rapidly decreases, and latchup resistance is improved.
In view of the foregoing, it is preferable to reduce the thickness of p
−
epitaxial layer
3
a
in order to improve the effect of reduced substrate resistance by p
+
silicon substrate
1
a
. In other words, the effect of an epitaxial wafer becomes more conspicuous as the epitaxial layer becomes thinner.
As the epitaxial layer becomes thinner, however, the following problems may arise.
As shown in
FIG. 18
, p-type impurity region
2
a
is formed in the boundary portion between p
+
silicon substrate
1
a
and p
−
epitaxial layer
3
a
. P-type impurity diffuses from p
+
silicon substrate
1
a
containing a high concentration of p-type impurity into p
−
epitaxial layer
3
a
to form p-type impurity region
2
a
. Thus, the concentration of p-type impurity in p-type impurity region
2
a
gradually changes.
When p
−
epitaxial layer
3
a
is made thinner in order to increase the effect of the epitaxial wafer as described above, p-type impurity region
2
a
reaches the high concentration region at the bottom portion of n-well
4
, changing the distribution of impurity concentration of n-well
4
significantly. Thus, breakdown voltage between p-type source/drain regions
8
a
,
8
b
and p
+
silicon substrate
1
a
decreases and a punch-through phenomenon is more likely to occur.
SUMMARY OF THE INVENTION
The present invention was made to solve such problems as stated above. An object of the present invention is to improve latchup resistance while preventing a punch-through phenomenon.
The semiconductor device in accordance with the present invention is provided with a low specific resistance semiconductor substrate of a first conductivity type having a main surface, an epitaxial layer, a first active region of the first conductivity type, a second active region of a second conductivity type, and an impurity region of the first conductivity type. The ep

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