Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-23
2001-08-21
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06279143
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to computer-aided circuit design systems and, more particularly, to a method and apparatus for creating a database which may be used for determining the design quality of network nodes in an integrated circuit.
BACKGROUND OF THE INVENTION
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components comprised on a single semiconductor “chip” in which the components are interconnected to perform a given function. Typical examples of integrated circuits include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the integrated circuit by using very large scale integrated (VLSI) circuit design techniques to create a circuit schematic which indicates the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated by those skilled in the art, electronic devices include electrical analog, digital, mixed hardware, optical, electromechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit “modules” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules, including all of the components within the modules. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by “black boxes.” As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These “black box” representations, hereinafter called “modules”, will mask the complexities therein, typically showing only input/output ports.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems identify certain critical timing paths, and then evaluate the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc., subsequently purchased by Synopsis, Inc. PathMill is a transistor-based analysis tool used to find critical paths and to verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. One primary shortcoming of the PathMill program is that it does not analyze the circuits to determine the design quality of the circuits. Rather, PathMill performs a static timing analysis of a circuit using the netlist provided to PathMill. Furthermore, configuring PathMill to recognize various circuit characteristics is typically a very difficult task.
Accordingly, a need exists for a rules checking system that will allow circuits to be evaluated for design quality. The present invention provides a method and apparatus for building a database which can be utilized by such rules checking system to determine the design quality of circuits. The present invention works in conjunction with a tool such as PathMill to build the database of the present invention. Typically, such tools, including PathMill, receive a netlist and use the netlist to determine FET (field effect transistor) direction, node types, latches, dynamic gates, rise and fall times, etc. This information can be utilized by the present invention to build a database which can then be utilized by a rules checking program to determine design quality of FET-level circuits designed in accordance with VLSI techniques.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for generating a database to be utilized by a rules checker for evaluating a particular design, such as, for example, an integrated circuit design. The design to be evaluated comprises a plurality of elements coupled together by at least one node. The apparatus of the present invention comprises a computer running a database generation program which receives, as its input to the database generation program, information relating to characteristics of the elements and nodes. The database generation program utilizes the input to produce a data structure for each of the elements and nodes. These data structures comprise the database which can be utilized by the rules checker to evaluate the design.
In accordance with the preferred embodiment of the present invention, the input to the database generation program corresponds to the output of a timing analyzer program which is being executed by the computer. The design is an electrical circuit design and the output of the static timing analyzer program includes statistical information relating to the elements, and pointers relating to the locations of the elements in the electrical circuit design. The pointers relate to the locations of the elements in the circuit and typically denote locations of a source, a drain and a gate of a field effect transistor. The database generation program utilizes the statistical information and the pointers in generating the data structures of the elements.
The output of the timing analyzer also includes information relating to whether any of the nodes are tied to a voltage supply, and the database generation program preferably also utilizes this information in generating the data
Kok Jan
McBride John G
Hewlett--Packard Company
Phan Trong
LandOfFree
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