Method of fabricating dual damascene structure

Details Method of fabricating dual damascene structure Method of fabricating dual damascene structure

2000-04-25

2001-09-18

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S616000, C438S622000, C438S623000, C438S624000, C438S637000, C438S638000, C438S639000, C438S640000

Reexamination Certificate

active

06291333

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89106402, filed Apr. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for multilevel interconnects of a semiconductor device. More particularly, the invention relates to a method of fabricating a dual damascene structure.
2. Description of Related Art
In the development of semiconductor industry, an improvement in operation speed of the device has always been a technology that all semiconductor manufacturers are up to compete, as well as been a main criterion that consumers take into account when making a purchase. With a rapid development of an integrated circuit process, a resistance of a conductive line and a parasitic capacitance between the conductive lines are determined as two key factors among all factors for influencing the operation speed of the device. Accordingly, a metal layer having a low resistance, such as a copper layer can substitute an aluminum layer used in the conventional method for reducing the resistance of the conductive line. A low dielectric constant (k) material, such as a low k organic dielectric layer can substitute a silicon oxide layer used in the conventional method for reducing the parasitic capacitance between the conductive lines.
A typical metal interconnect process involves forming a metal plug in a dielectric layer, followed by forming an aluminum line over a substrate for connecting to the metal plug. Generally, a dual damascene technique is a metal interconnect process with a high reliability and low cost, while a material selection for the metal interconnect is not limited by etching process for the metal. Therefore, this technique is widely applied to the manufacture of the copper line to reduce the resistance of the conductive line, and to further improve the operation speed and quality of the IC device. As there is a demand for a high operation speed of the device, fabricating the dual damascene with the low k material layer has been practiced in the metal interconnect process of the semiconductor industry.
FIG. 1
is a schematic, cross-sectional diagram illustrating a conventional dual damascene structure. Referring to
FIG. 1
, a via opening
112
is formed in a dielectric layer
104
, while a trench
110
is formed in a dielectric layer
108
. The via opening
112
and the trench
110
are then filled with a metal layer
114
to form a dual damascene structure.
As a conventional means to control a depth of the trench
110
, a silicon nitride layer
106
is formed between the dielectric layers
104
and
108
to serve as a stop layer during an etching process for forming the trench
110
.
However, the silicon nitride layer
106
has a dielectric constant of about 7, so a large parasitic capacitance easily occurs at areas, such as corners
118
of the trench
110
and the via opening
112
, where the silicon nitride layer
106
makes a direct contact with the metal layer
114
. This leads to a resistance-capacitance (RC) time delay and affects an operation efficiency of the device.
Moreover, as an integration of the device increases, the parasitic capacitance between two metal layers becomes more serious. Therefore, in a deep sub-micron process and below, a low k material is commonly used to form an inter-metal dielectric (IMD) layer in order to reduce the RC time delay derived from the parasitic capacitance.
The photoresist layer is commonly made of a polymer, while the common low k material is the organic polymer. So, when a photoresist layer that patterns the trench
110
is removed, an oxygen plasma can damage the low k organic dielectric layers,
108
and
104
. As a result, the low k organic dielectric layers,
108
and
104
on sidewalls of the trench
110
and the via opening
112
begin to absorb water, resulting a poisoned issue when the metal layer
114
is deposited.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating dual damascene structure for preventing a poisoned via or a poisoned trench.
The invention further provides a method of fabricating dual damascene structure for reducing a parasitic capacitance, while improving the operation efficiency of the device.
As embodied and broadly described herein, the invention provides a fabrication method for a dual damascene structure, which method forms a silicon oxide layer, a stop layer, a low k organic dielectric layer, and a cap layer are formed in sequence on a substrate. A trench is formed in the cap layer and the low k organic dielectric layer, while a via opening is formed in the stop layer and the silicon oxide layer. A part of the stop layer is removed to form a cavity below the low k organic dielectric layer, followed by forming spacers on sidewalls of the trench and the via opening for filling the cavity. The trench and the via opening are then filled with a copper layer to form a dual damascene structure.
According to the present invention, a part of the stop layer below the low k organic dielectric layer is removed, so that a cavity is formed between the low k organic dielectric layer and the silicon oxide layer. The spacer is made of a fluorinated polyarylethers (Flare) layer, while the Flare layer is formed by spin on coating method. Since the Flare layer is formed by spin on coating, it has an excellent gap fill capability for completely filling the cavity.
The cavity between the low k organic dielectric layer and the silicon oxide layer is filled with the spacer which is made of a Flare layer, so that the spacer can isolate the stop layer from the metal layer to avoid a direct contact therebetween. Since the Flare layer has a dielectric constant far smaller than that of the silicon nitride stop layer, the spacer can isolate the metal layer from the stop layer to reduce the RC time delay.
According to the present invention, the trench is formed in the low k organic dielectric layer, followed by filling the trench with the metal layer to form the metal line. Since the low k organic dielectric layer has a low dielectric constant, the RC time delay effect is reduced, while the efficiency of the device is improved.
Also, the low k organic dielectric layer is covered by the boron nitride cap layer and the spacer. In the step of removing the photoresist layer which forms the trench pattern, the boron nitride cap layer prevents the low k organic dielectric layer from absorbing water. Furthermore, the spacer is excellent anti-absorptive for water. Therefore, this prevents the low k organic dielectric layer which is located on the sidewall of the trench from releasing the absorbed water, when the trench is filled with the metal layer. This solves a poisoned issue caused by absorbing water moistures.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6027577 (2001-03-01), Wang et al.
patent: 6027993 (2000-02-01), Ueda
patent: 6071806 (2000-06-01), Wu et al.
patent: 6080655 (2000-06-01), Givens et al.
patent: 6140226 (2000-10-01), Grill et al.
patent: 6225204 (2001-05-01), Wu et al.

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