Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-09-30
2001-06-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S057000, C326S028000
Reexamination Certificate
active
06246264
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit for generating output signals as a function of input signals. The circuit serves as a part of a driver configuration for an output driver and ensures that data are output at an instant when they are regarded as valid.
Output drivers of various types occupy a central function as a component part of integrated semiconductor circuits. As a result of higher clock and data rates in integrated semiconductor circuits, the requirements with regard to the switching speed and a reliable voltage supply are also increasing. The high current pulses at output drivers and at the voltage supply, that are produced in connection with high clock rates and that lead to potential fluctuations in oscillatory systems, can in some instances cause malfunctions in other circuit sections of a semiconductor memory. Oscillatory systems are produced for example by line inductances of leads, bonding wires or lead frames in conjunction with capacitances on the chip.
Problems can arise, in particular, if the signal which enables an output driver and a datum to be applied to the output driver have different propagation times. This problem is present primarily in the case of clocked high-speed memory modules in which the memory access is triggered asynchronously with respect to the clock signal which enables the output driver. If the output driver is enabled too early, there is the risk that the datum to be output is not yet valid and changes its state during the enabled state of the driver. In such a case, a corresponding switching transistor of the output driver switches twice in direct succession, which, at high clock rates even of single switching operations, leads to even higher rates of current rise or in other words steeper current rises. Added to this is the fact that the output driver does not switch from the high-impedance state in the case of the second switching operation, rather at least one switching transistor is already in the on state in other words in the conducting state. In the event of a state change, this switching transistor must be put into the off state as rapidly as possible, which engenders additional current pulses which amplify the above-mentioned effect. The disturbances and irregularities produced in this way result in potential fluctuations at the terminals of the output driver or of the supply voltage which are significantly higher than in the case of a normal, single switching operation.
Attempts have previously been made to limit the rates of current rise which are caused by switching operations of output drivers, and likewise to reduce the inductances on the chip in terms of their magnitude. However, the technical possibilities are limited in this context. In earlier DRAM architectures, in particular fast-page-mode DRAMs and extended-data-out DRAMs with fixed access cycles, a validity signal is generated which enables the output driver only when valid data are present. It is thus ensured that only a single switching operation of the output driver takes place. What this presupposes is a certain memory access time which elapses starting from the triggering of the data access and by which the enabling of the output driver is delayed. In the case of higher and variable frequencies of the access cycle, however, there is the risk that the signal which disables the output driver after a data access and the memory access time overlap temporally, which thus leads to a defective functioning of the output driver. In the case of modern DRAMs (dynamic random access memories), in particular SDRAMs (synchronous DRAMs) and other forms of clocked DRAMs, a temporal overlap of the memory access time and of a clock signal which enables the output driver and disables it again is possible in a certain range. Therefore, a simple control of the data access which stipulates the access cycle and thus the activation of the output driver in terms of instant and duration is no longer appropriate, without there being the risk of multiple switching operations during an access cycle.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit for generating output signals as a function of input signals which overcomes the above-mentioned disadvantages of the heretofore-known circuits of this general type and in particular it is an object to provide a circuit configuration which is suitable for driving an output driver of a clocked DRAM-type semiconductor memory in the course of a memory access, so that a reliable operation is possible in the case of a variable clock frequency.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit for generating output signals as a function of input signals, including:
a first terminal for receiving a first input signal and a second terminal for receiving a second input signal, each of the first and second input signals having an active state and an inactive state;
a first output, connected to the first terminal, for supplying a first output signal having an active state and an inactive state and being derived from the first and second input signals;
a second output, connected to the first terminal, for supplying a second output signal having an active state and an inactive state;
a first storage device having a first input connected to the second terminal for receiving the second input signal and having an output, connected to the first output, for supplying an output signal having an active state and an inactive state, the storage device being configured such that the output signal of the output of the first storage device has an active state as soon as an active signal is present at the first input of the storage device, such that, in the event of the output signal of the first storage device being in the active state, the first output signal is switched from the inactive state to the active state at a first instant in the event of a last occurring transition selected from the group consisting of a transition of the first input signal from the inactive state to the active state and a transition of the second input signal from the inactive state to the active state, when the first input signal is in the active state, and such that the second output signal is switched from the inactive state to the active state at a second instant in the event of a transition of the first input signal from the inactive state to the active state.
In accordance with another feature of the invention, the first storage device is configured such that the first output signal is switched from the active state to the inactive state in the event of a transition of the first input signal from the active state to the inactive state immediately following the first instant.
In accordance with yet another feature of the invention, the first storage device is configured such that the first output signal is switched from the active state to the inactive state in the event a transition of the first input signal from the active state to the inactive state immediately following the first instant or in the event of a transition of the second input signal from the active state to the inactive state depending on which transition occurs last.
In accordance with a further feature of the invention, the first storage device is configured such that the first output signal and/or the second output signal remains in the active state during a fixed time period and subsequently changes to the inactive state.
In accordance with yet a further feature of the invention, the first storage device is configured such that the fixed time period is at least as long as is required by components, to be connected to the first output, to reliably identify a transition of the first output signal between the active state and the inactive state.
In accordance with another feature of the invention, the first storage device is configured such that the second output signal is switched from the active state to the inactive state in the event of a transition of the first in
Cho James H
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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