Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-11-19
2001-08-07
Paladini, Albert W. (Department: 2831)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C174S262000, C257S700000, C257S786000, C361S760000
Reexamination Certificate
active
06271478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic element such as a semiconductor chip having connection electrodes arranged in the form of an area array or a semiconductor device having external connection terminals arranged in the form of an area array, such as in a regular lattice form or in a regular staggered manner.
2. Description of the Prior Art
In modern semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced to compensate for a lack of space for forming electrodes by arranging electrodes as an area array on the electrode-forming surface of a semiconductor chip.
FIG. 11
illustrates an example in which a semiconductor chip
4
is mounted on a circuit board
5
relying on an ordinary flip-chip connection. The semiconductor chip
4
has electrodes
6
arranged on the peripheral edges thereof. Circuit patterns
7
are connected to every electrode
6
on a single plane.
FIG. 12
illustrates the arrangement of lands
8
on a circuit board for mounting a semiconductor chip, and the arrangement of circuit patterns
7
drawn from the lands
8
. In this example, the lands
8
are arranged in two sequences, each circuit pattern
7
is drawn running between the lands; i.e., the circuit pattern
7
is drawn from every land
8
on a single surface.
When the electrodes are arranged in many sequences in the longitudinal and transverse directions on the electrode-forming surface, however, it becomes no longer possible to take out the wirings toward the outer side from every land on the surface though it may vary depending upon the distance between the lands and the number of the lands.
In order to solve this problem, a method has been proposed according to which the circuit board for mounting a semiconductor chip is formed in many layers, and circuit patterns of the laminated circuit boards are suitably arranged to electrically connect all electrodes of the semiconductor chip to the circuit patterns.
FIG. 13
illustrates an example where a semiconductor chip
4
, on which the electrodes
6
are arranged as an area array, is mounted on a multi-layer circuit board. By using this multi-layer circuit board, it is possible to electrically connect every electrode
6
to the circuit patterns
7
,
7
a
even though the semiconductor chip
4
has electrodes
6
arranged as an area array. In
FIG. 13
, reference numeral
7
a
denotes a circuit pattern of an inner layer,
5
a
to
5
d
denote first to fourth circuit boards, and reference numeral
9
denotes external connection terminals.
When the semiconductor chip having electrodes arranged as an area array is to be mounted on the circuit board, only about two circuit boards must be laminated one upon the other provided the number of the electrodes is not very large. However when the semiconductor chip has as may pins as, for example, 30×30 pins or 40×40 pins, six to ten circuit boards must be laminated one upon the other.
When a plurality of circuit boards, on which the circuit patterns are very densely formed, are to be laminated to make a multi-layer circuit board, there will be employed a high-density wiring method such as build-up method. However, these methods have serious problems in regard to yield of the products, reliability and the cost of production. That is, when many circuit boards are to be laminated one upon the other, the boards should be successively laminated in such a manner that electrical connection must be accomplished through the vias formed in each board between the circuit patterns and between the circuit patterns across the boards. Therefore, a high degree of precision would be required. However, at present, such methods do not offer a high degree of reliability. Furthermore, when many boards are laminated, it is required that none of the boards is defective, involving a further increased technical difficulty.
SUMMARY OF THE INVENTION
To produce a multi-layer circuit board maintaining a good yield, therefore, a reduction in the number of wiring layers would be an effective solution.
The present invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip, having as many as 40×40 pins arranged in the form of an area array, on the side of the mounting surface, or such as a semiconductor device having electrodes arranged in the form of an area array, on the side of the mounting surface.
Thus an object of the present invention is to provide a multi-layer circuit board for mounting such a semiconductor chip or a semiconductor device, despite a decreased number of circuit boards being laminated one upon the other, which features an improved yield of production of the multi-layer circuit board and which can be used as a highly reliable product.
The present invention provides a multi-layer circuit board formed by laminating a plurality of circuit boards each having:
lands and/or vias arranged in many number in the form of an area array on a surface of the side on which an electronic part is mounted; and
circuit patterns having the ends on one side thereof connected to said lands and/or vias and having the ends, on the other side thereof, that are drawn from a region where said lands and/or vias are arranged in the form of an area array under such a condition that four or more circuit patterns are passed between the lands and/or vias at both ends by removing an intermediate land and/or via from the consecutively arranged three lands and/or vias; wherein
circuit patterns formed on a first circuit board on the surface of the side where said electronic part is mounted, are connected to every land positioned on the outermost side of the lands arranged in the form of an area array, and are connected to the lands alternatingly selected from the lands of the second sequence and the third sequence of the inner side;
circuit patterns formed on a second circuit board are connected to every via electrically connected to the lands of the second sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the fourth sequence and the fifth sequence on the first circuit board;
circuit patterns formed on a third circuit board are connected to every via electrically connected to the lands of the third sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the sixth sequence and the seventh sequence on the first circuit board; and
circuit patterns formed on a fourth circuit board are connected to every via electrically connected to the lands of the eighth sequence and the ninth sequence on the first circuit board.
The invention further provides a multi-layer circuit board formed by laminating, in many layers, the circuit boards having circuit patterns arranged in the same manner as the circuit patterns formed on said first to third circuit boards repetitively and in the same manner as said first to third circuit boards, and further laminating a circuit board having circuit patterns arranged in the same manner as the circuit patterns on said fourth circuit board.
REFERENCES:
patent: 4202007 (1980-05-01), Dougherty et al.
patent: 5467252 (1995-11-01), Nomi et al.
patent: 5650660 (1997-07-01), Barrow
patent: 5812379 (1998-09-01), Barrow
patent: 6107685 (2000-08-01), Nishiyama
patent: 0 308 714 (1989-03-01), None
patent: 0 351 184 (1990-01-01), None
patent: 0 814 643 (1997-12-01), None
Horiuchi Michio
Takeuchi Yukiharu
Takubo Chiaki
Paladini Albert W.
Pennie & Edmonds LLP
Shinko Electric Industries Co. Ltd.
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