Processor which can favorably execute a rounding process...

Details Processor which can favorably execute a rounding process... Processor which can favorably execute a rounding process...

1999-09-20

2001-05-22

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S551000, C708S552000

Reexamination Certificate

active

06237084

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor that performs processing according to instruction sequences that are stored in a ROM or the like.
2. Background of the Invention
In recent years, there has been a visible increase in the use of application software that can interactively reproduce various kinds of data, such as video data, still image data, and audio data, that have been compressed according to techniques such as frame encoding, field encoding, or motion compensation. As such software has been developed, there has been increasing demand for multimedia-oriented processors that can efficiently execute the software. These multimedia-oriented processors are processors designed with a special architecture to facilitate programming, such as the compression and decompression of video and audio data. The high-speed processing required for handling video data is the matrix multiplication of compressed data that has N*N matrix elements with coefficient data that also has N*N matrix elements. Representative examples of compressed data that has N*N matrix elements are the luminescence block composed of 16*16 luminescence elements, the blue color difference block (Cb block) composed of 8*8 color difference elements, and the red color difference block (Cr block) composed of 8*8 color difference elements used in MPEG (Moving Pictures Experts Group) techniques. The matrix multiplication for compressed data referred to here is performed very frequently when executing the approximation calculations for an inverse DCT (Discrete Cosine Transform) in image compression methods such as MPEG and JPEG (Joint Photographic Experts Group).
The following is a description of conventional multimedia-oriented processors that can perform high-speed matrix multiplication. The basic architecture of conventional multimedia-oriented processors is provided with a sum-product result register (hereinafter simply referred to as an MCR register) as hardware, and is provided with an instruction set that includes a “MOV MCR,**” transfer instruction for transferring a sum-product value.
An example of the hardware construction of a conventional multimedia-oriented processor is shown in FIG.
1
. As shown in
FIG. 1
, the arithmetic logic unit (hereinafter, “ALU”)
61
performs the multiplication of an element Fij that forms part of the compressed data and an element Gji that forms part of the coefficient matrix in accordance with a multiplication instruction. The ALU
61
also reads the sum-product value stored in the sum-product result register
62
, adds the multiplication result of Gji*Fij to the read sum-product value, and has the result of this addition stored in the sum-product result register
62
. By repeating the above calculation, a sum-product value is accumulated in the sum-product result register
62
. Once the multiplication has been performed a predetermined number of times, the programmer issues a sum-product value transfer instruction. By issuing a transfer instruction, the accumulated value in the sum-product result register
62
is transferred to the general registers, and is used as the matrix multiplication result for one row and one column. By performing N*N iterations of the above processing, the matrix multiplication of N*N compressed data and an N*N coefficient matrix can be completed.
When a conventional multimedia-oriented processor is used, however, positive correction saturation operations for amending the sum-product value pose many difficulties for programmers.
Positive conversion processing refers to the conversion of a sum-product value that is a negative value into either zero or a positive value. Normally, compressed data is expressed as a coded relative value that reflects the relation of the present value to the preceding and succeeding values. As a result, there are many cases when the sum of products for each element in the compressed data and the corresponding coefficients is a negative value. Most reproduction-related hardware, such as displays and speakers, however is only able to process uncoded data, so that when the sum-product values are to be reproduced, it is first necessary to perform positive conversion processing.
Saturation calculation processing refers to processing that sets all values that exceed a given range (or, in other words, which are “saturated”) at a predetermined value. This is to say, when an element that includes an erroneous bit generated during transfer is used in a sum-product calculation as part of the sum-product processing for compressed data, there is an increase in the probability of the sum-product value exceeding a value that can be expressed by the stated number of bits. Since most reproduction-related hardware is only physically capable of reproducing uncoded data with a fixed valid number of bits, such as eight bits, saturation processing is required to convert the sum-product value into a value that can be expressed using the valid number of bits.
It has been conventional practice to perform this kind of positive value conversion processing and saturation calculation processing by converting the-sum-product value using a subroutine that corrects the sum-product value. An example of a subroutine that corrects the sum-product value is explained below. In this example, the register width and the calculation width of the calculation unit are 32 bits, with the width of the MCR being 32 bits, and the sum-product value being expressed as a coded 16-bit integer. The data that can be handled by the reproduction-related hardware needs to be expressed using uncoded 8-bit integers. This subroutine is set as using the data register D
0
for storing the calculation result. Each instruction is expressed using two operands, with the left and right operands being respectively called the first and the second operands. The second operand is used both to indicate the transfer address of a transfer instruction and the storage address of an arithmetical instruction.
Instruction 1: MOV MCR,D
0
Instruction 2: CMP 0XFFFF
—
8000,D
0
Instruction 3: BCC CARRY
Instruction 4: MOV 0x0000
—
00000,D
0
Instruction 5: BRA END
CARRY:
Instruction 6: CMP 0x0000
—
00FF,D
0
Instruction 7: BCS END
Instruction 8: MOV 0x0000
—
00FF,D
0
END: (end of positive conversion saturation calculation processing)
Describing the above instructions in order, Instruction 1, “MOV MCR,D
0
”, transfers the stored value of the MCR register into the data register D
0
. Instruction 2, “CMP 0xFFFF
—
8000,D
0
”, compares the value in the data register with the immediate “0xFFFF
—
8000”, where “0x” shows that the value is given in hexadecimal. This comparison is performed by subtracting the immediate “0xFFFF
—
8000” given in the first operand from the stored value of the data register D
0
given in the second operand.
The sixteenth bit of the immediate “0xFFFF
—
8000” in Instruction 2 is the code bit used for a 16-bit coded integer, so that when the stored value of the data register D
0
is greater that the immediate “0xFFFF
—
8000”, this shows that the value stored in the MCR is a negative number.
On the other hand, when the stored value of the D
0
register is less than “0xFFFF
—
8000”, this shows that the value stored by the MCR is a positive number. If this number is a positive number, a carry is performed and the carry flag in the flag register is set.
The letter “B” in the “BCC” in Instruction 3 stands for “Branch”, while the letters “CC” stand for “Carry Clear”.
When the comparison in Instruction 2 finds that the stored value of the register D
0
is less than the immediate “0xFFFF
—
8000”, a branch is performed to Instruction 6 which has the label “CARRY”. Conversely, when the comparison in Instruction 2 finds that the stored value of the register D
0
is greater than the immediate “0xFFFF
—
8000”, Instruction 4, “MOV 0x0000
—
0000,D
0
” transfers the value zero into the register D
0
, amending the sum-product value to zero. After this amendment, the unconditional branch “BRA END” in Instruction 5 is performed to transfer the processing

Affiliated with

Also associated with

Rating

Processor which can favorably execute a rounding process... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor which can favorably execute a rounding process..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor which can favorably execute a rounding process... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2534261