Structure for laterally diffused metal-oxide semiconductor

Details Structure for laterally diffused metal-oxide semiconductor Structure for laterally diffused metal-oxide semiconductor

1999-03-18

2001-09-04

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S305000, C257S306000, C257S330000, C257S333000, C257S335000

Reexamination Certificate

active

06285059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process of producing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, and, more particularly, to a structure of an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up.
2. Description of the Prior Art
The LDMOS (Laterally Diffused Metal-Oxide Semiconductor) is usually used in high-voltage integrated circuits and may generally be manufactured using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. Hence, a commonly used high-voltage element for these circuits is the laterally diffused Metal-Oxide transistor (LDMOS). Conventional LDMOS structures are first discussed to establish a basic understanding of the present invention.
For example,
FIG. 1
shows a cross-sectional view of the structure of a conventional LDMOS transistor. The LDMOS transistor has a P-type substrate
10
, a V-shaped trench
11
, a P-type body region
12
, a N
+
drain region
15
, gate oxide
16
, and an oxide layer
17
. In this structure, the V-shaped trench
11
is used to reduce the dimension of the entire LDMOS transistor.
The N
+
source region
13
, the P-type body region
12
, and the P-type substrate
10
form a vertical parasitic PNP transistor. And the vertically projecting area of the N
+
source region
13
is relatively large, thus the leakage caused by the parasitic PNP transistor is relatively large and its propensity to cause latch-up problems is a drawback.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming an LDMOS transistor that substantially has reduced dimensions, reduced leakage, and a reduced propensity to latch-up.
According to
FIG. 2
, the LDMOS transistor of the present invention includes the following portions. They are P substrate
20
, silicon oxide
22
, N-well
23
,
23
A and
23
B, P-well
24
,
24
A and
24
B, oxide layer
26
and N+-type doped polysilicon
28
.
Generally the lightly doped portion is doped with dopants of the conductivity type. There is a second doping concentration, which is less than the first doping concentration. Consequentially a main portion of said first drain/source region is formed within the semiconductor layer. Therefore the main portion neighbouring the field insulating region/the oxide top surface and adjacent the lightly doped portion. Also the main portion disposed above the deep portion as well as the main portion is doped with dopants of the conductivity type and owns to a third doping concentration, which is less than the first doping concentration and is greater than said second doping concentration.
Consequently a main portion of the second drain/source region adjacent the lightly doped portion of the second drain/source region is formed. The main portion of the first drain/source region is formed at the same time as the main portion of said second drain/source region. Finally steps of forming a second drain/source region further comprise the step of forming a deep portion of the second drain/source region within the semiconductor layer and is spaced from the field insulating region/the oxide top surface by the lightly doped portion and the main portion.
In one embodiment, the object of the present invention is to provide a method of producing an LDMOS transistor. The above objects are fulfilled by providing a method of producing an LDMOS transistor on a substrate of a first conductivity type.


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