Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-13
2001-01-16
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S264000
Reexamination Certificate
active
06175133
ABSTRACT:
This application claims the benefit of Korean Application No. 96-70176 filed on Dec. 23, 1996, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory cell and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving the erase function and the topology of the memory cell.
2. Discussion of Related Art
Many studies have been made on semiconductor flash memory cells to fabricate highly integrated devices through simple processes. Related art has been disclosed in U.S. Pat. No. 5,070,032. In a conventional structure of a semiconductor flash memory cell, a device acts as an isolation layer as well. The isolation layer in this structure is formed by depositing an oxide layer on a buried data line. For example, cross-sectional views of a conventional flash memory cell in different directions are illustrated in FIG.
1
. In a method of fabricating the conventional flash memory cell as shown in
FIG. 1
, a buried data line
18
having an n
+
-type conductivity is formed on a semiconductor substrate
10
by ion-implantation. A high temperature and low pressure dielectric (HLD) layer and a device isolation layer (for example, an oxide layer) are then formed on the substrate
10
including the buried data line
18
to separate an active region from a field region.
Subsequently, a gate oxide layer
11
and a first polysilicon layer are formed on the entire surface of the substrate and then patterned to form a floating gate
12
. The floating gate
12
is insulated by an oxide layer formed by oxidation. A second polysilicon layer is deposited on the entire surface of the substrate and then patterned to form a control gate
13
.
The control gate
13
is insulated by a first insulating layer. A third polysilicon layer is deposited thereof and patterned to form an erase gate
14
. A second insulating layer is further deposited on the entire surface of the substrate. Accordingly, gates and contact holes are formed at portions for desired contact points. Thereafter, the flash memory cell is completed by forming a passivation layer
16
of boronphosphosilicate glass (BPSG) on a metal line
15
.
In programming the aforementioned flash memory cell, a high voltage is applied to the control gate and the data line, and electrons are injected into the floating gate at the edge of the gate insulating layer. To erase the programmed data in the flash memory cell, the electrons in the floating gate are removed through the insulating layer between the floating gate and the erase gate.
However, in the conventional flash memory cell, planarization of the memory cell is very difficult because of a step coverage generated by an erase gate formed on a device isolation oxide layer. Moreover, complex etching and plug processes are necessary to form the erase gate.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a flash memory cell and a method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a flash memory cell substantially downsized by a trench used in isolating each cell.
Another object of the present invention is to provide a flash memory cell reducing a step coverage by forming an erase gate on an isolation layer located in a trench-forming portion, thereby reducing a height of the erase gate.
Still another object of the present invention is to provide a flash memory cell having a highly improved erase function by contacting a floating gate to the upper and lower lateral end portions of the erase gate and making a larger contact area.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of fabricating a flash memory cell includes the steps of the steps of forming a buried data line in the substrate, forming an insulating layer on the substrate including the buried data line, forming an erase gate on the insulating layer, forming an isolation layer by etching the insulating layer with the erase gate as a mask, forming a floating gate having a indentation at least, the indentation of the floating gate corresponding to the erase gate, and forming a control gate on the floating gate.
In another aspect, the method of fabricating a flash memory cell having a substrate includes the steps of forming a buried data line in the substrate, forming an insulating layer on the substrate including the buried data line, forming an erase gate on the insulating layer, forming an isolation layer by etching the insulating layer with the erase gate as a mask, forming a first floating gate pattern having a indentation at least, the indentation of the first floating gate pattern corresponding to the erase gate, forming a control gate on the first floating gate pattern, and forming a floating gate having a indentation at least, the indentation of the floating gate corresponding to the erase gate.
In a further aspect, a flash memory cell includes a substrate, first and second buried data lines in the substrate, an isolation layer on the substrate, a floating gate including an indentation at least on the substrate between the first and second buried data lines, an erase gate over the isolation layer, a part of the erase gate being inserted into the indentation, and a control gates on the floating gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5268319 (1993-12-01), Harari
patent: 5455792 (1995-10-01), Yi
patent: 5544103 (1996-08-01), Lambertson
patent: 5554553 (1996-09-01), Harari
patent: 5643814 (1997-07-01), Chung
patent: 5686332 (1997-11-01), Hong
patent: 5965913 (1999-10-01), Yuan et al.
Booth Richard
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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