Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-04-24
2001-03-06
Monin, Jr., Donald L. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S763000, C257S770000
Reexamination Certificate
active
06198143
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a manufacturing method of highly refractory titanium silicide, and more particularly, to highly refractory titanium silicide used, for example, for formation of conductive layers on surfaces of gate electrodes source-drain regions and of salicide transistors or highly refractory interconnections in other semiconductor devices, and a manufacturing method thereof.
2. Description of the Background Art
Titanium silicide (mainly TiSi
2
) has the lowest resistivity among other high melting point metal silicide such as of titanium (Ti), molybdenum (Mo), and tungsten (W). Therefore, titanium silicide is among hopeful materials for highly refractory interconnections of various types in semiconductor devices. Among the others, salicide (
S
elf-
Ali
gned Sili
cide
) has attracted particular attention for its application to transistors.
A salicide transistor is constituted by forming a high melting point metal silicide film only over the respective surfaces of a gate electrode and source-drain regions of an MOS (Metal Oxide Semiconductor) field effect transistor. The salicide transistor is characterized by the feature that the metal silicide film which has been selectively formed thereon lowers resistivity where it has been applied.
A cross sectional structure of a conventional salicide transistor is shown in FIG.
1
. Referring to that view, there is shown a polycrystalline silicon gate electrode (referred to as “gate electrode” hereinafter) formed on a semiconductor substrate
1
with a gate insulating film
2
interposed therebetween. On both sides of the gate electrode
3
there are provided sidewalls
4
, outside of which diffusion layers
5
are formed in surface of the semiconductor substrate
1
to be source/drain regions.
At the surfaces of the gate electrode
3
and diffusion layers
5
there are formed a metal silicide film
6
made up of a compound of silicon and a refractory metal such as titanium, tungsten, molybdenum or the like. Respective device formation regions are separated by a device isolating insulating film
7
and surfaces of the formed devices are covered with an interlayer insulating films
8
. The interlayer insulating film
8
is provided with contact holes
9
in the areas over the gate electrode
3
and the diffusion layers
5
, immediately under which there are formed impurity diffused layers
10
. Additionally, metal interconnection layers
11
as of aluminum alloy are provided in the respective contact holes
9
.
It is desirable to use titanium as a referectory metal for forming the metal silicide film
6
, because the resistivity of titanium silicide is very low, that is, one-tenth of or less than that of other metal silicides.
Now, a manufacturing process of the salicide transistor will be described in the case where the metal silicide film
6
is formed of titanium silicide with reference to
FIGS. 2A
to
2
E.
Initially, with reference to
FIG. 2A
an MOS type LDD (Lightly Doped Drain) structure is formed according to the manufacturing process of the general MOS type LDD structure transistor. That is, a transfer gate oxide film
2
is first formed on a p-type semiconductor substrate by the so-called LOCOS (
Loc
al
O
xidation of
S
ilicon) with a device isolating insulating film
7
surrounding the same. Thereafter, polysilicon is deposited over the entire surface of the transfer gate oxide film
2
to a certain film thickness by low pressure CVD, and then formed into a gate electrode
3
by photoetching. Subsequently, n-type impurities such as phosphorus ion are implanted in surface of the semiconductor substrate
1
with the gate electrode
3
as mask to form a diffusion layer
5
a
of low concentration. Furthermore, an insulating film made of silicon dioxide or the like is deposited over the entire surface of the semiconductor substrate
1
by CVD and formed into sidewalls
4
by vertical anisotropic etching. Additionally, n-type impurities such as arsenic ion are then implanted in the surface of the semiconductor substrate
1
with the gate electrode
3
and the sidewalls
4
as mask to form further diffusion forming layer
5
b
of high concentration. Usually, heat treatment at above 900° C. is done for the activation of the implanted impurities, and thus the structure shown in
FIG. 2A
is completed.
Secondly, a titanium film
12
of a predetermined thickness is formed over the entire surface of the resulting MOS type LDD structure by sputtering or the like (FIG.
2
B). This titanium film
12
is generally formed to a thickness of 10 to 100 nm.
Following the above, heat treatment at 600° C. to 700° C. is done in nitrogen atmosphere. This heat treatment may also be done in vacuum or argon atmosphere. At this moment, mono-silicide or disilicide of titanium, i.e. TiSi or TiSi
2
is formed in the areas where the titanium film
12
contacts with any silicon surface, or at the surfaces of the gate electrode
3
and the diffusion layers
5
which have remained uncovered by the insulating films. On the other hand, the titanium film
12
over the regions covered with the silicon oxide films, or on the surfaces of the device isolating insulating film
7
and the sidewalls
4
remains unreacted or is reacted with nitrogen to form titanium nitride (TiN). Therefore, by removing the TiN and unreacted Ti with a proper solution such as mixture of sulfuric acid and hydrogen peroxide solution, titanium silicide can be left formed only over the gate electrode
3
and the diffusion layers
5
to form source/drain regions (FIG.
2
C). Meanwhile, the titanium silicide at this moment comprises TiSi as well as TiSi
2
.
Further heat treatment at about 800° C. for a predetermined time in nitrogen atmosphere (vacuum or argon atmosphere is also possible) enables a complete titanium disilicide (TiSi
2
) layer
13
(referred to simply as “titanium silicide layer
13
” hereinafter) to be formed.
Next, an interlayer insulating film
8
made of ailicate glass is deposited by CVD and then annealing at temperatures of 800° C. to 1,000° C. is done (FIG.
2
D). This annealing is indispensable to planalize the interlayer insulating film
8
by reflow, for the sake of enhancing the reliability of a metal interconnectin layer
11
formed thereon.
Subsequently, contact holes are opened by, for example, etching in predetermined portions over the gate electrode
3
and the diffusion layers
5
, through which impurities of the same conductivity type as that of diffusion layers
5
or n-type (such as phosphorus) are implanted into the semiconductor substrate
1
.
Subsequently, further heat treatment at 800° C. to 1,000° C. is done to thermally diffuse the impurities implanted immediately under the contact holes
9
, thereby forming impurity diffused layers
10
(FIG.
2
E). This process enables the n-type impurity diffused layers
10
to be formed under the contact holes even when they have been opened in the areas a little shifted from the diffusion layers
5
to cover the device isolating insulating films
7
so that the contact resistance therein can be reduced. Also, this process has the effect to decrease the junction leakage current in PN junctions which may be a problem encountered, for example, when the concentration of the diffusion layers
5
immediately under the contact holes
9
is not sufficient. Accordingly, this process is called SAC (Self-Aligned Contact) due to the resulting self-alignment.
Finally, a metal interconnection layer
11
is formed of aluminum or the like thereby to complete the manufacturing of a salicide transistor (FIG.
2
F).
In the salicide transistor formed as described above with the use of titanium silicide, when formed consistently to have good quality, the silicide film can reduce resistivity in the gate electrode
3
and the diffusion layers
5
down to one-tenth or less than that of other metal suicides due to its low resistivity. Therefore, an MOS type transistor of higher performance can be obtained.
Application of titanium silicide cannot be limited
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Monin, Jr. Donald L.
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