Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-05-03
2001-07-31
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
Reexamination Certificate
active
06269041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of pseudo static random access memory and, more particularly, to an embedded auto-refresh circuit to refresh static random access memory cells without the associated processing system being halted.
2. Description of Related Art
Conventionally, the Static Random Access Memory (SRAM) cell is typically configured to a Six-Transistor SRAM cell, as shown in
FIG. 6
, or a Resistive-Load SRAM cell, as shown in FIG.
7
. In addition,
FIG. 8
shows a Four-Transistor pseudo SRAM cell, which is able to save about half the layout area as compared to the Six-Transistor SRAM, and does not need an additional process to form a resistor as compared to the Resistive-Load SRAM. Furthermore, the Four-Transistor pseudo SRAM cell is provided with a better data stability as compared to the Dynamic Random Access Memory (DRAM). Therefore, the above Four-Transistor pseudo SRAM cells are widely used in electronic circuitry. However, it is known that the electric charge in the drain of such a Four-Transistor pseudo SRAM cell is prone to disappear due to sub-threshold leakage. As such, it is necessary to refresh the Four-Transistor pseudo SRAM cells in every predefined period of time in order to ensure the integrity of data.
A memory circuit constituted by the above Four-Transistor pseudo SRAM cell is shown in FIG.
9
. As shown, there are a plurality of cells
91
arranged in a matrix form. The cells
91
of each row are connected to a word line (WL)
92
, while the cells
91
of each column are connected to a bit line pair consisting of a bit line (BL)
931
and an inverted bit line ({overscore (BL)})
932
. To access memory, a pre-charge circuit
95
is enabled to charge the bit line
931
and inverted bit line
932
to a voltage level of logic “1” to clear the original data on the bit line pair, so as to avoid data overwriting in the subsequent memory access. The address from an address bus
96
is decoded by an address decoder
94
to select the cells
91
on a word line
92
to perform a read or write operation.
A block diagram of a typical system configured by the above Four-Transistor pseudo SRAM and the timing diagram thereof are shown in FIG.
10
and
FIG. 11
, respectively. As shown in
FIG. 10
, an additional refresh circuit
97
is employed to carry out the memory refresh operation. That is, when the memory system
98
is required to be refreshed, the refresh circuit
97
stops the current procedure in the processing system
99
and asserts the R/{overscore (W)} signal to issue a pseudo read operation to the memory system
98
for memory refresh. It is obvious that the processing system
99
has to be halted when the memory system
98
is in refresh, and thus a lot of bandwidth that can be used for data processing is wasted. The drawback of wasting bandwidth is even more troublesome as the semiconductor manufacturing process develops into the deep sub-micron technique, hence the sub-threshold leakage is increasing. Therefore, there is a need for the above Four-Transistor pseudo SRAM to be improved.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an embedded auto-refresh circuit for automatically refreshing pseudo static random access memory cells without the need of additional pseudo read cycles, such that no system resources are wasted.
To achieve the above object, the embedded auto-refresh circuit in accordance with the present invention includes a shift register and an auto-refresh generation circuit. The shift register is driven by a clock signal to perform shift operations. The auto-refresh generation circuit has a pre-charge and refresh signal generator driven by the clock signal to generate a refresh signal and a pre-charge signal. The pre-charge signal has a first pulse and a second pulse. In a memory access cycle, a plurality of memory cells on a word line determined by the refresh signal and the shift register are refreshed by a pseudo read operation based on the first pulse and the refresh signal, and then a general random memory access process is performed by taking the second pulse as a pre-charge signal.
REFERENCES:
patent: 5033026 (1991-07-01), Tsujimoto
patent: 5289424 (1994-02-01), Ito et al.
patent: 5517454 (1996-05-01), Sato et al.
Chen Thomas
Wang Thomson
Lowe Hauptman & Gilman & Berner LLP
Phan Trong
Sunplus Technology Co. Ltd.
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