Vertical type insulated gate transistor

Details Vertical type insulated gate transistor Vertical type insulated gate transistor

1999-11-04

2001-03-06

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S342000

Reexamination Certificate

active

06198129

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a structure of a power MOS transistor suitable for use in a motor control circuit or a power circuit or the like and a method of manufacturing the same.
2. Description of the Related Art
Various structures have heretofore been proposed as the structure of a power MOS transistor. However, the structure of a VDMOS (Vertical Diffusion MOS) transistor corresponding to a vertical type MOS transistor, featuring that it causes current to flow in the vertical direction of a semiconductor substrate, is generally basic to the structure of the power MOS transistor. This is because since the entire substrate is formed as a drain structure, the resistance thereof becomes low and a large current flow is provided and it is apt to withstand high voltages and reduce thermal resistance.
FIG. 1
is a cross-sectional view of a conventional VDMOS transistor and shows an N channel type. A drain region of the VDMOS transistor is formed of an N type semiconductor substrate
1
, whereas each source region thereof is composed of an N+ diffusion layer
6
, a P well layer
2
and a P+ diffusion layer
7
for applying a voltage.
The operation of the VDMOS transistor is as follows: When a desired voltage is applied to a gate electrode
5
, a current flows from the N type semiconductor substrate
1
used as the drain to the N+ diffusion layer
6
used as the source through the surface of a semiconductor disposed below the gate electrode
5
. The amount of the current at this time is controlled by gate and drain voltages in a manner similar to the normal type MOS transistor.
With the spread of application areas of a VDMOS transistor, there has recently been a demand for a VDMOS transistor made more powerful in performance. A reduction in on resistance, which is the utmost important characteristic of the power MOS transistor, is required to meet such a demand. The on resistance of the VDMOS transistor consists of a series of a channel resistance of a MOS transistor and a resistance (lying in the vertical direction) of an N type semiconductor substrate. However, the shorter the length of a gate of the transistor, the more the channel resistance can be reduced. It is thus quite natural that a reduction in on resistance should be achieved by shortening the gate length and reducing the resistance of the substrate.
As is however apparent from
FIG. 1
, the gate length of the VDMOS transistor is determined according to a junction depth of each P well diffusion layer
2
formed over the M type semiconductor substrate
1
. Since the P well diffusion layers
2
are respectively formed from gate ends on the source sides of the VDMOS transistor, a channel region is determined depending on the length of each P well diffusion layer
2
, which extend in the transverse direction thereof. It is thus necessary to form the P well diffusion layers
2
shallowly for the purpose of a reduction in gate length.
On the other hand, a high withstand voltage characteristic is known as one feature of the VDMOS transistor. While a withstand voltage of about 1000V is required according to purposes, a withstand voltage of about a few 100V is required even in the normal case. The P well diffusion layers
2
are formed deep for the purpose of high withstanding and the shape of each P well diffusion layer
2
by which the withstand voltage is determined, is set as smooth as possible, thereby reducing the curvature thereof and avoiding the concentration of an electric field on each P well diffusion layer
2
. It is necessary to select a substrate having a high resistance or resistivity of about 100 &OHgr;·cm for the purpose of high withstanding from the viewpoint of a depletion layer even in the case of the substrate resistance.
SUMMARY OF THE INVENTION
As described above, it becomes necessary to deepen the P well diffusion layers and increase the resistance of the N type semiconductor substrate with a view toward maintaining a high withstand voltage characteristic. However, a problem arises in that this is contrary to the reduction in on resistance.
In order to solve the problem of a difficulty in reducing the on resistance, the present invention provides a vertical type insulated gate transistor wherein a P type impurity region for relaxing or reducing an electric field is formed between the N type semiconductor substrate and the corners of the P well diffusion layers both employed in the conventional VDMOS transistor.
According to the present invention, since an electric field produced between a drain and P well diffusion layers is reduced owing to a P type impurity diffusion layer (field relaxation layer) provided in the neighborhood of the corners of the P well diffusion layers, a transistor can withstand high voltages. Thus, since the P well diffusion layers can be shallowed in depth, the VDMOS transistor can be reduced in gate length. Further, since the depth of each P well diffusion layer and the expansion of a depletion layer therefrom, which are parameters for determining the thickness of the semiconductor substrate, are also reduced owing to a shallow junction between the P well diffusion layers and the semiconductor substrate, the thickness of the substrate can be formed thinner. It is therefore possible to reduce on resistance while a high withstand voltage characteristic is being held.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.


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patent: 63-150970 (1988-06-01), None
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