Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-29
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S181000
Reexamination Certificate
active
06288962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a system using the same, and particularly, relates to a structure of an input/output interface of a semiconductor device for forming a high speed system. More particularly, the invention relates to a structure of an interface which does not cause ringing even if a signal level transition time is reduced.
2. Description of the Background Art
FIG. 21
schematically shows an example of a structure of a data processing system in the prior art. In
FIG. 21
, a processing unit (CPU) PC and a plurality of memory devices M
1
-Mn are commonly connected to a data bus DB. Processing unit (CPU) accesses memory devices M
1
-Mn via data bus DB. In recent years, the data transfer speed of memory devices M
1
-Mn has been increased in accordance with increase in internal operation speed of processing unit (CPU) PC.
FIG. 22
shows an example of a structure of a data output portion of one bit in memory devices M
1
-Mn. In
FIG. 22
, a data output circuit includes a logic determining portion
900
receiving an output enable signal OE and an internal data signal DATA, to determine a logic level of output data, a timing adjusting portion
902
for adjusting timing of the output signal of logic determining portion
900
, and an output portion (driver)
904
for driving a transfer line
906
in accordance with the output signal of timing adjusting portion
902
.
Logic determining portion
900
includes an inverter
900
a
inverting output enable signal OE, an NAND circuit
900
b
receiving output enable signal OE and internal data DATA, and an NOR circuit
900
c
receiving the output signal of inverter
900
a
and internal data DATA.
In a general memory system, as shown in
FIG. 21
, a plurality of memory devices M
1
-Mn are coupled to data bus DB. Therefore, output enable signal OE is used for preventing conflict between data on data bus DB (data transfer line
906
). In this logic determining portion
900
, when output enable signal OE is at L-level, the output signal of NAND circuit
900
b
is at H-level, and the output signal of NOR circuit
900
c
is at L-level so that transfer of internal data DATA is not performed. When output enable signal OE attains H-level, NAND circuit
900
b
and NOR circuit
900
c
operate as inverters, each of which inverts internal data DATA and applies the inverted data to timing adjusting portion
902
in the next stage.
Output driver
904
includes a P-channel MOS transistor (insulated gate field effect transistor)
904
a
and an N-channel MOS transistor
904
b.
Timing adjusting portion
902
includes a first timing adjusting circuit
902
a
for adjusting the timing of the output signal of NAND circuit
900
b
, to apply a drive signal to a gate of P-channel MOS transistor
904
a
of output driver
904
, and a second timing adjusting circuit
902
b
receiving the output signal of NOR circuit
900
c
, for adjusting timing thereof to apply the timing-adjusted signal to a gate of N-channel MOS transistor
904
b
of output driver
904
. Timing adjusting portion
902
adjusts the timing of the signals applied from logic determining portion
900
for avoiding such a situation that both MOS transistors
904
a
and
904
b
of output driver
904
are simultaneously turned on to cause flow of a through-current. More specifically, first timing adjusting circuit
902
a
adjusts a waveform of its output signal such that the rising of the output signal may be sharp for achieving faster turn-off of MOS transistor
904
a
of output driver
904
, while the falling of the output signal may be slowed. Second timing adjusting circuit
902
b
likewise adjusts the timing so as to make the falling of its output signal sharp for achieving faster turn-off of MOS transistor
904
b
of output driver
904
, and to slow down the rising of the output signal. Thereby, the MOS transistors in output driver
904
to be turned off rapidly attain the off state, and paths of a through-current are rapidly cut off for preventing occurrence of the through-current.
When output enable signal OE is at L-level, the output signal of NAND circuit
900
b
is at H-level, and the output signal of NOR circuit
900
c
is at L-level. In output driver
904
, both MOS transistors
904
a
and
904
b
are off, and the output circuit is at an output high impedance state. Thus, this data output circuit is a tristate output circuit.
FIG. 23
shows an example of a structure of an input portion for one-bit data. In
FIG. 23
, the input circuit includes an NOR circuit
910
which receives write data sent through transfer line
906
and a chip select signal CS, and an inverter
912
which inverts and transmits the output signal of NOR circuit
910
to an internal circuit. Chip select signal CS designates that the memory device is selected and has to be received write data. By applying chip select signal CS to NOR circuit
910
, it is determined whether the input signal is to be activated or not. Further, the level for determining the logic level applied through transfer line
906
is adjusted by adjusting the input logic threshold voltage. Inverter
912
in the next stage adjusts delay of rising and falling of the write data applied from NOR circuit
910
. NOR circuit
910
is formed of MOS transistors, which receive on their respective gates the signal sent through transfer line
906
and chip select signal CS. The gate of each MOS transistor is electrically isolated from other internal nodes by a gate insulating film. Therefore, transfer line
906
is not electrically terminated, and is electrically floated.
In the data processing system, memory devices are arranged on a board, and are connected together via on-board interconnection lines. Data bus DB shown in
FIG. 21
is on-board interconnection lines, and other control signals, a clock signal or the like are transmitted via on-board interconnection lines. The on-board interconnection line is greater in line width than internal interconnection lines of the memory devices, and has a relatively large parasitic impedance and a relatively large parasitic capacitance (e.g., parasitic capacitance with respect to the board).
FIG. 24
schematically shows a distribution of parasitic impedances on the transfer line. In
FIG. 24
, the transfer line has a parasitic resistance Ru per unit length, an inductance Lu per unit length and a parasitic capacitance Cu per unit length. Parasitic resistance Ru and inductance Lu are connected in series. Parasitic capacitance Cu is connected between the transfer line and a ground node (board). In the case where the impedances are distributed on the transfer line as described above, a characteristic impedance Z can be represented by the following formula, assuming that resistance value R can be neglected.
Z={square root over ((Lu·Cu))}
A propagation delay time tpdu per unit length of the transfer line having the characteristic impedance Z is expressed by the following formula:
tpdu={square root over ((Lu·Cu))}
The output circuit shown in
FIG. 22
must perform fast transfer of data via the transfer line having characteristic impedance Z. By increasing the size (ratio of gate width to gate length) of MOS transistors
904
a
and
904
b
included in output driver
904
shown in
FIG. 22
, or by reducing the equivalent resistances (channel resistances in the on-state) of the MOS transistors, the level transition time of the transfer signal becomes short, and the data transfer speed can be increased. However, if such fast data transfer is performed, the parasitic inductance and parasitic capacitance of the transfer line would cause signal reflection on the end, i.e., on the data input side to cause ringing if the equivalent resistances of MOS transistors
904
a
and
904
b
of the output driver are not matched with the impedance of the transfer line.
FIG. 25
shows a reflection coefficient and transmission coefficient of the transfer line. In
FIG. 25
, a transfer line
920
having a characteristic impedance Z
1
is connected to
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran M.
LandOfFree
Semiconductor device allowing fast signal transfer and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device allowing fast signal transfer and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device allowing fast signal transfer and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2530860