Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1998-08-04
2001-01-02
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S379000, C361S091500
Utility Patent
active
06169312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static protection circuit for use in a semiconductor integrated circuit device.
2. Description of the Prior Art
When a person touches an input or output terminal of a semiconductor integrated circuit device such as an LSI with his hand or finger, abnormal electrostatic charge may be applied to the circuit inside, destroying the semiconductor integrated circuit device. Such application of electrostatic charge from a human hand or finger usually occurs when a semiconductor integrated circuit device is not in operation, for example during the mounting of the semiconductor integrated circuit device onto a circuit board or in the process preparatory thereto.
To prevent destruction caused by electrostatic charge, a semiconductor integrated circuit device usually incorporates a simple protection circuit.
FIG. 7
illustrates a conventional example of such a protection circuit. In
FIG. 7
, numeral
100
represents an I/O (input/output) circuit including a buffer and other components, and numeral
101
represents a signal line leading to a pad
102
. The pad
102
is connected to an external output terminal. Numeral
103
represents an N-channel MOS transistor having its drain connected to the signal line
101
, having its source connected to ground, and having its gate also connected to ground.
In this circuit, when abnormal electrostatic charge is applied to the pad
102
from the outside, punch-through occurs between the drain and the source of the MOS transistor
103
(i.e. instead of the MOS transistor
103
being turned on in the normal manner, a high voltage applied between the source and the drain causes the source-drain channel to conduct and thereby causes a current to flow therethrough), with the result that the electrostatic charge is bypassed to ground. In this way, the I/O circuit
100
and other internal circuits are protected from destruction.
However, in this conventional example, when abnormal electrostatic charge is applied, the high electrostatic charge applied between the drain D and the gate G of the transistor
103
may destroy the gate insulating film of the transistor
103
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel and effective static protection circuit that is so designed that its protection transistor is not destroyed by abnormal electrostatic charge.
To achieve the above object, according to one aspect of the present invention, a static protection circuit for use in a semiconductor integrated circuit device is provided with: a first MOS transistor of a P-channel type whose source-drain channel is connected between a signal line leading to an external connection terminal and ground; and a second MOS transistor of a P-channel type having its drain connected to the gate of the first MOS transistor, having its source connected through a first resistor to a power source line, and having its gate connected through a second resistor to ground.
In this structure, when abnormal electrostatic charge is applied from the external connection terminal, punch-through occurs between the source and the drain of the first MOS transistor, and causes a current to flow from the signal line to ground, thereby discharging the abnormal electrostatic charge quickly. In addition, the gate of the first MOS transistor is brought into an electrically floating state (i.e. a cut-off state) by the second MOS transistor, and therefore the above-mentioned abnormal charge is not applied between the source and the gate of the first MOS transistor. Thus, the gate insulating film of the first MOS transistor is not destroyed.
On the other hand, as for the second MOS transistor, when abnormal electrostatic charge is applied to the power source line, a high voltage appears between the power source line and ground. However, the first and second resistors bear a portion of this high voltage, and accordingly reduce the source-gate voltage of the second MOS transistor. Thus, the gate insulating film of the second MOS transistor is not destroyed, either.
According to another aspect of the present invention, a static protection circuit for use in a semiconductor integrated circuit device is provided with: a first MOS transistor of an N-channel type whose source-drain channel is connected between a signal line leading to an external connection terminal and ground; and a second MOS transistor of an N-channel type having its drain connected to the gate of the first MOS transistor, having its gate connected through a first resistor to a power source line, and having its source connected through a second resistor to ground. Also in this structure, the transistors are protected from destruction.
According to still another aspect of the present invention, a static protection circuit for use in a semiconductor integrated circuit device is provided with: a first MOS transistor of a P-channel type whose source-drain channel is connected between a signal line leading to an external connection terminal and a power source line; a second MOS transistor of an N-channel type whose source-drain channel is connected between the signal line and ground; a third MOS transistor of a P-channel type having its drain connected to the gate of the first MOS transistor, having its source connected through a first resistor to the power source line, and having its gate connected through a second resistor to ground; and a fourth MOS transistor of an N-channel type having its drain connected to the gate of the second MOS transistor, having its gate connected through a third resistor to the power source line, and having its source connected through a fourth resistor to ground.
In this structure, when abnormal electrostatic charge is applied to the signal line, punch-through occurs in both of the first and second MOS transistors, and thereby the abnormal electrostatic charge is bypassed. Thus, it is possible to achieve more secure protection than in the previously-described structures. Moreover, the gates of the first and second MOS transistors are connected to the third and fourth MOS transistors so that they will not receive the abnormal voltage, and therefore the gate insulating films of the first and second MOS transistors are not destroyed. On the other hand, even if abnormal electrostatic charge is applied to the power source line, the voltage applied to the gate insulating films of the third and fourth MOS transistors are reduced by the first to fourth resistors, and therefore the gate insulating films of these MOS transistors are not destroyed, either.
REFERENCES:
patent: 62-105462 (1987-05-01), None
Arent Fox Kitner Plotkin & Kahn PLLC
Prenty Mark V.
Rohm & Co., Ltd.
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