Trench non-volatile memory cell

Details Trench non-volatile memory cell Trench non-volatile memory cell

1999-08-18

2001-01-30

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S322000

Reexamination Certificate

active

06180980

ABSTRACT:

FIELD OF THE INVENTION
The invention is related to a method of manufacturing a memory cell, and particularly to a method of manufacturing a non-volatile memory cell, such as EEPROM.
BACKGROUND
Non-volatile memory cells, including stacked gate and split gate, are well-known in the art. The split gate structure has better over erase control performance, simple circuit design and faster access speed.
A cross section of a conventional Flash EEPROM is shown in FIG.
1
. Drain impurity diffusion layer
16
and a source impurity diffusion layer
17
are formed on a main surface of the semiconductor substrate
10
and are spaced from each other by a predetermined distance with a channel region therebetween. The conventional Flash EEPROM further includes a floating gate electrode
13
formed on the channel region with a first gate oxide film
12
therebetween, a control gate electrode
15
formed on the floating gate electrode
13
with an insulating film
14
therebetween, an interlayer thermal oxide film
18
covering the semiconductor substrate
10
, floating gate electrode
13
and control gate electrode
15
, and an interlayer insulating film
19
covering the interlayer thermal oxide film
18
. Gate bird's beak oxide films
20
are formed at opposite ends of the first gate oxide film
12
and opposite ends of the insulating film
14
. The interlayer insulating film
19
contains an impurity such as boron or phosphorous. The purpose of the interlayer thermal oxide film
18
is to prevent the movement of the impurity (i.e., boron of phosphorous) of the interlayer insulating film
19
into the semiconductor substrate
10
, control gate electrode
15
or floating gate electrode
13
, and thus to prevent change of the electrical characteristics thereof.
After the final step of forming the interlayer insulating film
19
to cover the interlayer thermal oxide film
18
shown in
FIG. 1
, heat treatment by a reflow method is usually carried out to flatten the interlayer insulating film
19
. During this process as well as while thermally growing the thermal oxide layer
18
by means of wet oxidation, oxidizer (H.sub.2 O) penetrates the interlayer insulating film
19
and interlayer thermal oxide film
18
. This causes further oxidization between the semiconductor substrate
10
and the ends of the floating gate electrode
13
, and between the control gate electrode
15
and the floating gate electrode
13
. As a result, the gate bird's beak oxide films
20
are formed. Consequently, the lower end of the floating gate electrode
13
contacts the gate bird's beak oxide films
20
so that the lower end of the floating gate electrode
13
is oxidized to a large extent as compared with the other portions.
The gate bird's beak oxide film
20
can form either at the lower end of the floating gate
13
and the source impurity diffusion layer
17
, or at the lower end of the floating gate near the drain impurity diffusion layer
16
, or at both locations. In these cases, the conventional “beak” of the bird's beak is usually long and elongated, thus increasing the size of the cell and at the same time providing paths for current leakage and resulting, therefore, in low memory speed.
The formation of a conventional bird's beak in a polysilicon gate is better shown in
FIGS. 1
b
and
1
c
. In
FIG. 1
b
, layers of gate oxide
110
, polysilicon
120
and nitride
130
are successively formed on substrate
100
and then patterned with a photomask layer
140
to define the floating polygate region
160
. Subsequently, polysilicon layer
120
is oxidized, whereby gate bird's beaks
121
and
121
′ are formed as well known in the art. The prior art offers a method of implanting the polysilicon so as to decrease the growth of the protrusion of the gate bird's beak as shown by reference numerals
121
and
121
′ in
FIG. 1
c
to a smaller size and sharper shape shown by reference numerals
125
and
125
′. It will be known by those skilled in the art that the smaller the birds' beak, the smaller the encroachment under the polysilicon edge, and hence the smaller the impact on the electric-field intensity between the corner edge of the floating gate
129
and the control gate
180
of the completed cell structure shown in
FIG. 1
d
, and thus the faster the memory speed. (See S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era,” vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 438). It will also be appreciated that the smaller the bird's beak, the smaller the overall size of the memory cell, also contributing to the increased speed of the memory.
However, in the above-mentioned prior art, it is difficult to reduce the chip area occupied by the memory cells because all of the cells are built on the silicon surface.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the invention to provide a method of manufacturing a trench non-volatile memory cell, comprising the steps of:
providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate by silicon etching, said trench reaching down to the source region; growing a first isolation layer on the surface of the semiconductor substrate, and the bottom and sidewall of the trench; forming a hollow-shaped first conducting layer in the trench; performing thermal oxidation on the first conducting layer to form a bird's beak isolation layer and a floating gate, which are the oxidized and unoxidized part of the first conducting layer, respectively, wherein the floating gate has a peak; partially removing the first isolation layer and the bird's beak isolation layer to bare the surface of the semiconductor substrate, the peak and the sidewall of the trench; depositing a second conducting layer; patterning the second conducting layer to form a control gate; and defining a drain region in the semiconductor substrate.
It is another object of the invention to provide a trench non-volatile memory cell, comprising: a substrate; a source region defined in the substrate; a trench formed on the substrate and reaching down to the source region; a floating gate formed in the trench and having a peak; an isolation layer formed on the bottom and the sidewall of the trench, the surface of the substrate, and the peak; a bird's beak isolation layer formed on the non-peak part of the floating gate; a control gate formed on the isolation layer and the bird's beak isolation layer; and a drain region defined in the substrate and adjacent to the sidewall of the trench.
Since the trench non-volatile memory cell of the invention is built in the trench on the substrate, it is possible to reduce the chip area occupied by the memory cell. Thus, it is easier to scale down the memory circuit.


REFERENCES:
patent: 4641164 (1987-02-01), Dolny et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5929482 (1999-07-01), Kawakami et al.
patent: 5962893 (1999-10-01), Omura et al.
patent: 6091107 (2000-07-01), Amaratunga et al.

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