Clamping circuit for cell plate in DRAM

Details Clamping circuit for cell plate in DRAM Clamping circuit for cell plate in DRAM

1999-08-11

2001-05-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S189090

Reexamination Certificate

active

06236598

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to electronic circuits integrated on a semiconductor substrate. More particularly, this invention relates to circuits used to create reference biasing voltages for a common plate of a cell capacitor of a memory storage cell of a dynamic random access memory.
2. Description of the Related Art
FIG. 1
illustrates the general structure of an array of memory storage cells CELL
0
, CELL
1
, CELL
2
, and CELL
3
of a dynamic random access memory (DRAM). Each cell CELL
0
, CELL
1
, CELL
2
, and CELL
3
is formed of a single metal oxide semiconductor (MOS) transistor N
P
and a cell capacitor C
C
. The drain of the pass transistor N
P
is connected to a top plate of the cell capacitor C
C
. The source of the pass transistor N
P
is connected to one of the bit-lines BL
0
, BL
0
B, BL
1
, BL
1
B. The gate of the pass transistor N
P
is connected to one of the word-lines WL
0
and WL
1
. The commonly connected plates of all the cell capacitors C
C
is connected to a cell plate biasing voltage source V
P
. The voltage level of the cell plate biasing voltage source V
P
is designed to be an intermediate value between the voltage level of the power supply voltage source V
DD
and the ground reference point GND. The voltage level of the plate biasing voltage source V
P
is set such that the voltage developed across the cell capacitors is reduced.
When a cell is to have a bit of digital data written to or retrieved from a cell, one of the word-lines WL
0
or WL
1
is brought to a voltage level greater than the threshold voltage V
TH
of the pass transistor N
P
plus the voltage level present on either the drain or source of the pass transistor. The bit-lines BL
0
, BL
0
B, BL
1
, BL
1
B are pre-charged to a voltage level that is one half the value of the voltage level of the power supply voltage source V
DD
, if the memory cell is to have the bit of digital data retrieved from it. If the memory cell contains a high logic level (1), the voltage level of the top plate of the cell capacitor is approximately the voltage level of the power supply voltage source V
DD
. Conversely, if the memory cells contains a low logic level (0), the voltage level at the plate of the cell capacitor is approximately the voltage level of the ground reference point GND. When the pass transistor is activated, a charge flows to or flows from the top plate of the cell capacitor C
C
. The sense amplifier SA
0
or SA
1
senses and amplifies this charge flow and forces the bit-lines BL
0
, BL
0
B, BL
1
, BL
1
B to the appropriate voltage level (V
DD
or GND) dependent on the logic level stored at the top plate of the cell capacitance.
For writing a bit of digital data to the memory cell, the bit-lines BL
0
, BL
0
B, BL
1
, BL
1
B are pre-charged appropriately to the voltage level of the desired logic level (V
DD
or GND).
The appropriate word-line WL
0
or WL
1
is activated to turn on the pass transistor N
P
. The voltage present on the appropriate bit-line BL
1
, BL
1
B, BL
2
, or BL
2
B flows to charge or discharge the cell capacitor.
Refer now to
FIG. 2
for a discussion of a typical cell plate reference voltage generator of the prior art. The cell plate reference voltage generator includes a biasing circuit composed of MOS transistors N
10
, P
10
, N
11
and P
11
and an output buffer circuit composed of MOS transistors N
12
and P
12
. The biasing circuit is designed to provide adequate bias to the output circuit such that the cell plate reference voltage generator provides a desired cell plate reference voltage V
P
. In the circuit as shown, the ratio of the sizes of MOS transistors P
10
and N
11
is used to determine the right level of the cell plate reference voltage V
P
while the ratio of the sizes of MOS transistor N
10
and P
11
relative to those of MOS transistors P
12
and N
12
determines the static current of the cell plate reference voltage generator provided by MOS transistors N
12
and P
12
. If this static current is high, the cell plate reference voltage generator has low output impedance or high drive ability. Alternately, cell plate reference voltage generator has high output impedance or low drive ability, if the static current is low. To limit the stand-by power consumption of the DRAM chip the static current provided by the cell plate reference voltage generator must be kept low.
However, the low static current characteristic of the conventional cell plate reference voltage generator can create a severe problem during memory access. Referring to FIG.
1
and
FIG. 2
, during memory access all the memory cells connected to selected word-lines are enabled and may be accessed by corresponding bit-lines. That is, the current in the bit-lines may charge or discharge the storage capacitors of the selected memory cells when the corresponding access transistors are turned on as described above. Therefore, current surges flowing into and from the storage capacitors can occur in the period of memory write and read cycles. Voltage noise in the cell plate reference voltage V
P
will occur as a result of the cell plate reference voltage generator having less drive ability and not being able to provide adequate current to these storage capacitors.
This induced voltage noise may be lower or higher than the normal level of the cell plate reference voltage V
P
. It is known that memory cells that are not being access may be disturbed due to noise on their common plates of the cell capacitor C
C
that brings the cell plate reference voltage V
P
lower than the normal level. For any memory cell not being accessed, the gate of its pass transistor N
P
is connected to a grounded word-line, and, therefore, the pass transistor N
P
is turned off. Basically, negative voltage noise on the common plate of the cell capacitor can not charge or discharge the cell capacitor C
C
as long as the access transistor is kept off. As a result, the voltage on the storage node D
X
of the storage capacitor moves down with this noise that lowers the voltage level of the cell plate reference voltage generator for the same amount. Usually, the pass transistors N
P
in DRAMS are N-type MOS transistors. If a low voltage or zero voltage is stored in the memory cell not being accessed and the magnitude of the noise that lowers the voltage level of the cell plate reference voltage generator is greater than the threshold voltage V
TH
of its pass transistor N
P
, the pass transistor N
P
will turn on and introduce current from the connected bit-lines BL
0
, BL
0
B, BL
1
, BL
1
B to flow through the cell capacitor C
C
. Thus the memory cell is disturbed by the negative noise that lowers the voltage level of the cell plate reference voltage generator. The sub-threshold current of the pass transistor N
P
also increases even though the negative noise that lowers the voltage level of the cell plate reference voltage generator is not sufficient to completely turn on the pass transistor N
P
.
Two conventional techniques may be used to reduce disturbance effects caused by noise that lowers the voltage level of the cell plate reference voltage generator. The first technique is to implement pass transistors having a high threshold voltage V
TH
to increase noise margin. However, a pass transistor with a high threshold voltage level V
TH
will slow down memory access. The alternative is to apply a negative voltage to the unselected word-lines to reverse-bias these pass transistors N
P
, but that requires extra control circuitry in each decoder and driver connected to the word lines and consequently requires more area and consumes more power.
An example of the effect of the noise present at the cell plate reference voltage generation circuit is shown in FIG.
3
. In this example the memory cell CELL
1
of
FIG. 1
has a high logic level (1) present on the top plate D
1
of the cell capacitor C
C
and the memory cell CELL
0
has a low logic level (0) present on the cell capacitor. The voltage level present at the junction D
1
of the top plate of the cel

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