Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-24
2001-03-27
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S649000
Reexamination Certificate
active
06207987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more specifically to a semiconductor device ensuring the planarity of an interlayer insulating film and preventing displacement of an interconnection thereby achieving a high degree of integration.
2. Description of the Background Art
As one example of conventional semiconductor devices, a semiconductor device including an MOS transistor will be described with reference to the drawings. Referring to
FIG. 47
, a plurality of gate electrode portions
55
including a polycrystalline silicon film
55
a
, a tungsten silicide film
55
b
and a silicon oxide film
55
c
are formed on the surface of a silicon semiconductor substrate
51
with a gate insulating film
54
interposed therebetween. A pair of impurity diffusion layers
56
a
,
56
b
are formed at the surface of silicon semiconductor substrate
51
with one gate electrode portion
55
sandwiched therebetween. A pair of impurity diffusion layers
56
c
,
56
d
are formed at the surface of silicon semiconductor substrate
51
with another gate electrode portion
55
sandwiched therebetween. A sidewall insulating film
57
is formed on the both side surfaces of gate electrode portion
55
. Gate electrode portion
55
and a pair of impurity diffusion layers
56
a
,
56
b
constitute one MOS transistor. Further, gate electrode portion
55
and a pair of impurity diffusion layers
56
c
,
56
d
constitute another MOS transistor. Gate electrode portion
55
of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separating oxide film
53
that is formed in an element separating trench
52
at the surface of silicon semiconductor substrate
51
.
A silicon oxide film
58
is formed on silicon semiconductor substrate
51
to cover gate electrode portion
55
. On silicon oxide film
58
, a silicon oxide film doped with boron and phosphorous, that is, a BPSG (Boro-Phospho-Silicate-Glass) film
59
is formed. A silicon oxide film
60
is formed on BPSG film
59
. A plurality of second interconnection layers
62
including a polycrystalline silicon film
62
a
, a tungsten silicide film
62
b
and a silicon oxide film
62
c
are formed on silicon oxide film
60
. One second interconnection layer
62
is electrically connected to gate electrode portion
55
as a first interconnection layer by a polycrystalline silicon film filled in contact hole
61
a
that is formed in BPSG film
59
and silicon oxide films
60
,
58
. Another second interconnection layer
62
is electrically connected to impurity diffusion layer
56
b
by a polycrystalline silicon film filled in a contact hole
61
b
that is formed in BPSG film
59
and silicon oxide films
60
,
58
. A silicon oxide film
63
is formed on silicon oxide film
60
to cover second interconnection layer
62
. A BPSG film
64
is also formed on silicon oxide film
63
. A plurality of third interconnection layers
67
are formed on BPSG film
64
.
Third interconnection layers
67
are electrically connected to gate electrode portion
55
and impurity diffusion layers
56
c
,
56
d
by plugs
66
a
,
66
b
,
66
c
e.g. of tungsten filled in contact holes
65
a
,
65
b
,
65
c
that are formed in BPSG films
59
,
64
and silicon oxide films
63
,
60
,
58
. Third interconnection layer
67
is also electrically connected to second interconnection layer
62
by a plug
66
d
filled in a contact hole
65
d
that is formed in BPSG film
64
and silicon oxide film
63
. The conventional semiconductor device has such a configuration.
One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to
FIG. 48
, element separating trench
52
is formed at the surface of silicon semiconductor substrate
51
by prescribed photolithography and RIE (Reactive Ion Etching) methods. To fill element separating trench
52
, a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is then formed on silicon semiconductor substrate
51
by the CVD method. The silicon oxide film is polished by the CMP (Chemical Mechanical Polishing) method to form separating oxide film
53
in element separating trench
52
. Gate oxide film
54
having a film thickness of 5 to 15 nm is then formed on the surface of silicon semiconductor substrate
51
by the thermal oxidation method. On gate oxide film
54
, a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed. A plurality of gate electrode portions
55
as the first interconnection layers including polycrystalline silicon film
55
a
, tungsten silicide film
55
b
and silicon oxide film
55
c
are formed by the prescribed photolithography and RIE methods. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate
51
using gate electrode portion
55
as a mask, a region (not shown) of a comparatively low impurity concentration is formed.
To cover gate electrode portion
55
, a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is then formed on silicon semiconductor substrate
51
by the CVD method. The silicon oxide film is etched by the RIE method to form sidewall insulating film
57
on the both side surfaces of gate electrode portion
55
. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate
51
using sidewall insulating film
57
and gate electrode portion
55
as a mask, a region (not shown) of a comparatively high impurity concentration is formed. Thus, a pair of impurity diffusion layers
56
a
,
56
b
and a pair of impurity diffusion layers
56
c
,
56
d
. are respectively formed at the surface of silicon semiconductor substrate
51
with gate electrode potions
55
sandwiched therebetween. Thereafter, comparatively thin silicon oxide film
58
is formed on silicon semiconductor substrate
51
by the CVD method to cover gate electrode portion
55
. BPSG film
59
is formed on silicon oxide film
58
by the CVD method.
Referring to
FIG. 49
, BPSG film
59
is heated at a temperature of approximately 850° C. to locally planarize the surface of BPSG film
59
. In other words, BPSG film
59
is reflowed. Locally planarizeed BPSG film
59
is etched by the RIE method or a hydrofluoric acid solution to make BPSG film
59
thinner.
Referring to
FIG. 50
, comparatively thin silicon oxide film
60
is formed on BPSG film
59
by the CVD method. Then, contact hole
61
a
exposing the surface of tungsten silicide film
55
b
of gate electrode portion
55
and contact hole
61
b
exposing the surface of impurity diffusion layer
56
b
are formed in BPSG film
59
and silicon oxide films
60
,
58
by the prescribed photolithography and RIE methods. A polycrystalline silicon film, a tungsten silicide film and a silicon oxide film (they are not shown) are then formed on silicon oxide film
60
by the CVD method. Second interconnection layer
62
including polycrystalline silicon film
62
a
, tungsten silicide film
62
b
and silicon oxide film
62
c
is then formed by the prescribed photolithography and RIE methods.
Referring to
FIG. 51
, comparatively thin silicon oxide film
63
is formed on silicon oxide film
60
by the CVD method to cover second interconnection layer
62
. BPSG film
64
is then formed on silicon oxide film
63
by the CVD method.
Referring to
FIG. 52
, BPSG film
64
is heated at a temperature of approximately 800° C. to locally planarize the surface of BPSG film
64
. Thereafter, BPSG film
64
is etched by the RIE method or a hydrofluoric acid solution , if necessary, to further planalize the surface of BPSG film
64
.
Referring to
FIG. 53
, contact hole
65
a
exposing the surface of tungsten silicide film
55
b
of gate electrode portion
55
, contact holes
65
b
,
65
c
exposing the surfaces of impurity diffusion layers
56
c
,
56
d
,
Hardy David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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