Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-31
2001-09-25
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S628000, C438S643000, C438S644000, C438S687000
Reexamination Certificate
active
06294458
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor devices and, more particularly, to an inlaid interconnect feature with improved adhesion between conductor and dielectric materials.
RELATED ART
Integrated circuits are formed on semiconductor substrates using a number of different processing operations that create the transistor and interconnect elements. In order to access transistor elements associated with the semiconductor substrate, metal vias and interconnects are formed in dielectric materials as part of the integrated circuits. The inlaid metal vias and interconnects provide the means for transfer of electrical signals and power between transistors, internal circuits, circuits external to the die, and other aspects.
Semiconductor devices usually include a semiconductor device substrate, field isolation regions, and doped regions formed within the semiconductor device substrate. A gate dielectric layer overlies portions of the semiconductor device substrate, and a gate electrode overlies the gate dielectric layer. Spacers are formed adjacent the sidewalls of the gate electrode. A first interlevel dielectric layer (IDL) is patterned to form a contact opening that is filled with a contact fill material, and optionally a barrier layer. The barrier layer is typically a refractory metal, a refractory metal nitride, or a combination of refractory metals or their nitrides. The contact fill material typically includes tungsten, polysilicon, or the like. After depositing the barrier layer and the contact fill material, the substrate is polished to remove portions of the barrier layer and contact fill material not contained within the contact opening to form the conductive plug.
A first level interconnect is then formed overlying the interlevel dielectric (ILD) layer and the conductive plug. The first level interconnect can be formed using a combination of trench and polishing processes or, alternatively, using a combination of patterning and etching processes. If the first level interconnect is formed using copper, a barrier may be formed adjacent to the first level interconnect to reduce the migration of copper into surrounding materials. The first level interconnect is formed, for example, as a single inlaid structure. As such, the first level interconnect is created by first depositing a portion of a second ILD which is then etched to form a trench in which the material that makes up the first level interconnect is deposited. Once deposition of the first level interconnect occurs, a polishing process removes any excess material that remains outside of the trench formed.
Assuming that the first level interconnect has been formed as a single inlaid structure, the remainder of the second ILD is formed subsequent to the polishing step. An interconnect that can include a conductive barrier film and a copper material is then formed within the second ILD. The barrier film is typically a refractory metal, a refractory metal nitride, or a combination of refractory metals or their nitrides. The copper fill material is typically copper or a copper alloy, where the copper content is at least 95 atomic percent. The copper can be alloyed with magnesium, sulfur, carbon, or the like to improve adhesion, electromigration or other properties of the interconnect. Interconnects can alternatively be formed in other manners, for example, as a conductive plug in combination with a dual inlaid interconnect or as a lithographically patterned and etched interconnect.
Adhesion between various interconnect layers in a semiconductor device is an important characteristic. If adhesion between layers is inadequate in the device, problems are presented, such as delamination, separation of layers, inter-diffusion of layers, and other physical faults that can lead to decreased performance, electrical shorts, opens, and structural integrity concerns. Adequate adhesion between layers is, therefore, an objective in the semiconductor manufacture process.
Conventionally, various materials have been used as barrier layers in semiconductor devices. For example, barrier layers are typically formed atop surfaces of a dielectric layer prior to formation of a next conductive layer. Often, it is important, or at least beneficial, if the barrier layer employed in the application to prevent inter-diffusion between interconnect metals and dielectrics can also serve to increase the adhesion between the metal interconnect and dielectric. Furthermore, the barrier layer material can provide a seed layer for metal deposition to the surface of the dielectric, and act to keep the process chemistry from interaction with underlying layers. In typical inlaid Cu metal structures Ta or TaN forms the barrier layer between Cu and the dielectric trenches and vias.
In a conventional inlaid process forming an interconnect structure, a trench is formed in an interlevel dielectric (ILD) layer. The ILD layer is typically silicon dioxide (SiO2), doped silicon dioxide, an organic polymer, or some other dielectric material. A way of forming the SiO2 ILD is CVD or PECVD processes using tetraethyloxysilane or alternatively a process using tetraethyloxysilane in combination with a fluorine source to form fluorine containing SiO2 (FTEOS). In order to provide a barrier for the next metal layer on the ILD layer and within the trench and trench via (i.e., the “inlaid structure”) formed in the ILD layer, the barrier material, which can also serve to increase adhesion, is typically formed on the dielectric surface. A conventional example of the barrier layer is Ta or its nitride deposited on the surface of the ILD layer prior to the deposition of copper as the metal interconnect layer.
As is conventional, an inlaid interconnect structure is formed within the trench and via of the interlevel dielectric layer after the barrier layer is deposited. It is desirable that the barrier layer serve to prevent delamination and inter-diffusion of the metal layer. As mentioned, however, the conventional barrier layer materials have proven problematic, particularly when tantalum is interconnected with copper through trench and via structures in the interlevel dielectric layer, such as FTEOS. It has been experienced that the tantalum metal in such instances tends to delaminate from the ILD layer because of adhesion problems and that the metal material can inter-diffuse into the ILD layer and migrate causing electro-migration concerns.
The conventional process for the formation of the barrier layer in dual or single inlaid copper interconnects is to form a continuous Ta or TaN film, i.e. a barrier layer or film, on the ILD using a noble gas plasma to sputter metal atoms from a Ta target onto a semiconductor device substrate. The forming of Ta or TaN as a barrier layer is determined by the gas(es) in the vacuum vessel (“gas ambient”) in which the barrier layer formation occurs. For example, the conventional barrier layer for inlaid copper interconnects is formed using tantalum and argon gas combination or tantalum, argon and nitrogen gas combination in the presence of a plasma energized (sustained) by electric energy applied to the Ta sputter electrode. Alternatively, in addition to the Ta sputter electrode, other electrodes can be energized to assist (sustain) the plasma and direct ions. Examples of these are: power can be applied to the device substrate electrode to assist ion collection and a third electrode positioned to the periphery, but not between the Ta target and substrate, can be energized to increase the quantity of charged ions. The three power sources are identified as a metal sputtering DC power source, a radio frequency AC power source, and a wafer bias radio frequency power source. The resulting wafer from the process has a Ta or tantalum nitride surface portion, formed atop the dielectric material. This tantalum nitride or Ta surface atop the dielectric serves as a barrier layer for a next metal layer of copper deposited over the dielectric layer.
The tantalum barrier adhesion to the dielectric material exhibits the problems previou
Denning Dean J.
Garcia Sam S.
Pozder Scott K.
Zhang Jiming
Clingan, Jr. James L.
Motorola Inc.
Wilson Christian D.
Zarabian Amir
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